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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 24 | johboh | 1 | #include "../Include/CANdefs.h" |
| 2 | #include "../Include/stackTasks.h" |
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| 3 | #include "../Include/CAN.h" |
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| 4 | #include "../Include/uart.h" |
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| 5 | |||
| 6 | |||
| 7 | #ifdef USE_CAN |
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| 8 | |||
| 9 | |||
| 10 | |||
| 11 | |||
| 12 | /* |
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| 13 | * Function: canInit |
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| 14 | * |
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| 15 | * Input: none |
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| 16 | * Output: none |
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| 17 | * Pre-conditions: none |
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| 18 | * Affects: Changes can registers. |
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| 19 | * Depends: none. |
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| 20 | */ |
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| 21 | void canInit() |
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| 22 | { |
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| 23 | |||
| 24 | // 1. Ensure that the ECAN module is in Configuration mode. |
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| 25 | CANCON=0; |
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| 26 | |||
| 27 | CANCONbits.REQOP2=1; // Request configruation mode |
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| 28 | while(!CANSTATbits.OPMODE2); // Wait for configuration mode |
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| 29 | |||
| 30 | //2. Select ECAN operational mode. |
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| 31 | #ifdef CAN_ENCHANCED_MODE |
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| 32 | // Use Mode 1: Enchanged Legacy mode |
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| 33 | // ECANCON.MDSEL1:MDSEL0 = 1 |
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| 34 | ECANCONbits.MDSEL1 = 0; |
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| 35 | ECANCONbits.MDSEL0 = 1; |
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| 36 | #else |
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| 37 | // Use Mode 0: Legacy mode |
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| 38 | // ECANCON.MDSEL1:MDSEL0 = 0 |
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| 39 | ECANCONbits.MDSEL1 = 0; |
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| 40 | ECANCONbits.MDSEL0 = 0; |
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| 41 | #endif |
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| 42 | |||
| 43 | |||
| 44 | // BUFFERS |
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| 45 | |||
| 46 | // Make all programmable buffers receive buffers |
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| 47 | BSEL0 = 0x00; |
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| 48 | |||
| 49 | // Setup the receive buffers |
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| 50 | RXB0CON = 0; |
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| 51 | RXB1CON = 0; |
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| 52 | B0CON = 0; |
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| 53 | B1CON = 0; |
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| 54 | B2CON = 0; |
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| 55 | B3CON = 0; |
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| 56 | B4CON = 0; |
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| 57 | B5CON = 0; |
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| 58 | |||
| 59 | |||
| 60 | |||
| 61 | //3. Set up the baud rate registers. |
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| 62 | // Times for different time segments: |
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| 63 | // Sync_Seq + Prop_Seq + Phase_Seg1 + Phase_Seg2 = 8 |
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| 64 | // Sync_Seq = 2, Prop_Seq = 2, Phase_Seg1 = 2, Phase_Seg2 = 2 |
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| 65 | // BRGCON1.SJW1:SJW0 = 1 |
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| 66 | // BRGCON1.BRP5:BRP0 = CAN_BRP |
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| 67 | // BRGCON2.SEG2PHTS = 0 //Maximum PHEG1 |
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| 68 | // BRGCON2.SEG1PH2:SEG1PH0 = 1 |
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| 69 | // BRGCON2.PRSEG2:PRSEG0 = 1 |
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| 70 | // BRGCON3.WAKDIS = 1/0 1=Dsiable CAN bus wake up |
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| 71 | // BRGCON3.WAKFIL = 1/0 1=Use filter on wake up |
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| 72 | // BRGCON3.SEG2PH2:SEG2PH0 = 1 |
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| 73 | |||
| 74 | BRGCON1=0; |
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| 75 | |||
| 76 | // Sync_Seq = 2 x TQ = 1 |
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| 77 | BRGCON1bits.SJW1=0; |
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| 78 | BRGCON1bits.SJW0=1; |
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| 79 | |||
| 80 | // Setting BRP. |
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| 81 | BRGCON1=BRGCON1|CAN_BRP; |
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| 82 | |||
| 83 | // Maximum PHEG1 |
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| 84 | BRGCON2bits.SEG2PHTS = 1; |
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| 85 | |||
| 86 | // Phase_Seg1 = 2 x TQ = 1 |
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| 87 | BRGCON2bits.SEG1PH2 = 0; |
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| 88 | BRGCON2bits.SEG1PH1 = 0; |
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| 89 | BRGCON2bits.SEG1PH0 = 1; |
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| 90 | |||
| 91 | // Prop_Seq = 2 x TQ = 1 |
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| 92 | BRGCON2bits.PRSEG2 = 0; |
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| 93 | BRGCON2bits.PRSEG1 = 0; |
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| 94 | BRGCON2bits.PRSEG0 = 1; |
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| 95 | |||
| 96 | // Enableing bus wake-up |
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| 97 | BRGCON3bits.WAKDIS = 0; |
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| 98 | |||
| 99 | // Dont use filter when wakeup |
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| 100 | BRGCON3bits.WAKFIL = 0; |
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| 101 | |||
| 102 | // Phase_Seg2 = 2 x TQ = 1 |
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| 103 | BRGCON3bits.SEG2PH2 = 0; |
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| 104 | BRGCON3bits.SEG2PH1 = 0; |
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| 105 | BRGCON3bits.SEG2PH0 = 1; |
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| 106 | |||
| 107 | |||
| 108 | //4. Set up the filter and mask registers. |
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| 109 | |||
| 110 | // Disable all filters |
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| 111 | RXFCON0 = 0; |
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| 112 | RXFCON1 = 0; |
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| 113 | |||
| 114 | |||
| 115 | // No data byte filtering |
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| 116 | SDFLC = 0; |
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| 117 | |||
| 118 | // Setup filter/buffer association, two filters per buffer |
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| 119 | RXFBCON0 = 0x00; |
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| 120 | RXFBCON1 = 0x11; |
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| 121 | RXFBCON2 = 0x22; |
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| 122 | RXFBCON3 = 0x33; |
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| 123 | RXFBCON4 = 0x44; |
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| 124 | RXFBCON5 = 0x55; |
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| 125 | RXFBCON6 = 0x66; |
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| 126 | RXFBCON7 = 0x77; |
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| 127 | |||
| 128 | // Setup filter/mask association to Mask 0 |
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| 129 | MSEL0 = MSEL1 = MSEL2 = MSEL3 = 0; |
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| 130 | |||
| 131 | // Set Mask 0 to not mask any filter bit |
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| 132 | RXM0SIDH = 0xFF; |
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| 133 | RXM0SIDL = 0xE3; |
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| 134 | RXM0EIDH = 0xFF; |
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| 135 | RXM0EIDL = 0xFF; |
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| 136 | |||
| 137 | // Set I/O control CANTX pin will drive VDD when recessive |
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| 138 | CIOCON = 0x20; |
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| 139 | |||
| 140 | // Set interrupts |
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| 141 | // Diable transmit interrupt |
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| 142 | TXBIE = 0; |
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| 143 | |||
| 144 | //rx any interrupt |
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| 145 | PIR3 = 0; |
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| 146 | PIE3 = 0b00000011; |
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| 147 | |||
| 148 | // High interrupt |
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| 149 | IPR3 =0b00000011; |
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| 150 | |||
| 151 | // Programmable buffers interrupt |
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| 152 | BIE0 = 0xFF; |
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| 153 | |||
| 154 | //5. Set the ECAN module to normal mode or any other mode required by the application logic. |
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| 155 | #ifdef CAN_LOOPBACK_MODE |
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| 156 | // Use Loopback mode |
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| 157 | CANCON=0b01000000; |
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| 158 | #else |
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| 159 | // Use Normal mode |
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| 160 | CANCON=0b00000000; |
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| 161 | #endif |
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| 162 | |||
| 163 | while(CANSTATbits.OPMODE2); // Wait for configuration mode |
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| 164 | } |
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| 165 | |||
| 166 | |||
| 167 | /* |
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| 168 | * Function: canISR |
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| 169 | * |
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| 170 | * Input: none |
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| 171 | * Output: none |
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| 172 | * Pre-conditions: a call to canInit() |
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| 173 | * Affects: interrupt registers and receive data buffers |
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| 174 | * Depends: .. |
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| 175 | */ |
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| 176 | void canISR() |
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| 177 | { |
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| 178 | BYTE defECANCON; |
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| 179 | |||
| 180 | |||
| 181 | if (PIR3bits.RXBnIF==1 && PIE3bits.RXBnIE==1 || PIR3bits.RXB1IF==1 || PIR3bits.RXB0IF==1) |
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| 182 | { |
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| 183 | uartPutrs("canISR!"); |
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| 184 | |||
| 185 | |||
| 186 | // Save default ECANCON |
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| 187 | #ifdef CAN_ENCHANCED_MODE |
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| 188 | defECANCON=(ECANCON&0b00000)|0b10000; |
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| 189 | #else |
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| 190 | defECANCON=(CANCON&0b000)|0b000; |
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| 191 | #endif |
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| 192 | |||
| 193 | if (RXB0CONbits.RXFUL==1) |
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| 194 | { |
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| 195 | #ifdef CAN_ENCHANCED_MODE |
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| 196 | ECANCON = defECANCON|0b10000; |
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| 197 | #else |
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| 198 | CANCON = defECANCON|0b000; |
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| 199 | #endif |
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| 200 | |||
| 201 | canGetPacket(); |
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| 202 | RXB0CONbits.RXFUL=0; |
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| 203 | } |
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| 204 | else if (RXB1CONbits.RXFUL==1) |
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| 205 | { |
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| 206 | |||
| 207 | #ifdef CAN_ENCHANCED_MODE |
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| 208 | ECANCON = defECANCON|0b10001; |
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| 209 | #else |
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| 210 | CANCON = defECANCON|0b101; |
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| 211 | #endif |
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| 212 | |||
| 213 | canGetPacket(); |
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| 214 | RXB1CONbits.RXFUL=0; |
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| 215 | } |
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| 216 | #ifdef CAN_ENCHANCED_MODE |
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| 217 | else if (B0CONbits.RXFUL==1) { ECANCON = defECANCON|0b10010; canGetPacket(); B0CONbits.RXFUL=0; } |
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| 218 | else if (B1CONbits.RXFUL==1) { ECANCON = defECANCON|0b10011; canGetPacket(); B1CONbits.RXFUL=0; } |
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| 219 | else if (B2CONbits.RXFUL==1) { ECANCON = defECANCON|0b10100; canGetPacket(); B2CONbits.RXFUL=0; } |
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| 220 | else if (B3CONbits.RXFUL==1) { ECANCON = defECANCON|0b10101; canGetPacket(); B3CONbits.RXFUL=0; } |
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| 221 | else if (B4CONbits.RXFUL==1) { ECANCON = defECANCON|0b10110; canGetPacket(); B4CONbits.RXFUL=0; } |
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| 222 | else if (B5CONbits.RXFUL==1) { ECANCON = defECANCON|0b10111; canGetPacket(); B5CONbits.RXFUL=0; } |
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| 223 | #endif |
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| 224 | else {PIR3bits.RXBnIF=0; PIR3bits.RXB1IF=0; PIR3bits.RXB0IF=0; return;} |
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| 225 | |||
| 226 | // Restore mapping |
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| 227 | #ifdef CAN_ENCHANCED_MODE |
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| 228 | ECANCON = defECANCON; |
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| 229 | #else |
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| 230 | CANCON = defECANCON; |
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| 231 | #endif |
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| 232 | |||
| 233 | PIR3bits.RXBnIF=0; |
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| 234 | } |
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| 235 | |||
| 236 | } |
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| 237 | /* |
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| 238 | * Function: canGetPacket |
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| 239 | * |
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| 240 | * Input: none |
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| 241 | * Output: none |
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| 242 | * Pre-conditions: a call to canISR and an packet is available and banked to RXB0 |
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| 243 | * Affects: Calls canParse() function in main for parsing received packet. |
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| 244 | * Depends: none. |
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| 245 | */ |
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| 246 | void canGetPacket() |
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| 247 | { |
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| 248 | CAN_MESSAGE cm; |
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| 249 | |||
| 250 | // Set extended mode or not. |
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| 251 | cm.extended=RXB0SIDLbits.EXID; |
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| 252 | |||
| 253 | // Clear |
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| 254 | cm.ident[0]=cm.ident[1]=cm.ident[2]=cm.ident[3]=0; |
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| 255 | |||
| 256 | |||
| 257 | if (cm.extended==TRUE) |
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| 258 | { |
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| 259 | //Read extended ident. |
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| 260 | cm.ident[0]=RXB0EIDL; |
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| 261 | cm.ident[1]=RXB0EIDH; |
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| 262 | cm.ident[2]=(RXB0SIDL & 0b00000011)+((RXB0SIDL & 0b11100000)>3)+((RXB0SIDH & 0b00000111)<5); |
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| 263 | cm.ident[3]=RXB0SIDH>3; |
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| 264 | } |
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| 265 | else |
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| 266 | { |
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| 267 | //Read standard ident. |
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| 268 | cm.ident[0]=((RXB0SIDL & 0b11100000)>5)+(RXB0SIDH>2); |
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| 269 | cm.ident[1]=RXB0SIDH>5; |
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| 270 | } |
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| 271 | |||
| 272 | // Data length |
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| 273 | cm.data_length=RXB0DLC; |
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| 274 | |||
| 275 | // Data one bye one, for speed |
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| 276 | cm.data[0]=RXB0D0; cm.data[1]=RXB0D1; |
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| 277 | cm.data[2]=RXB0D2; cm.data[3]=RXB0D3; |
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| 278 | cm.data[4]=RXB0D4; cm.data[5]=RXB0D5; |
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| 279 | cm.data[6]=RXB0D6; cm.data[7]=RXB0D7; |
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| 280 | |||
| 281 | |||
| 282 | //Call main parser |
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| 283 | canParse(cm); |
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| 284 | |||
| 285 | //RXBnCON.RXFUL to know if there actually is a message. |
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| 286 | //RXB0 och RXB1 (0 <= n <= 1) |
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| 287 | //RXBnCON.FILHIT do determine filter hit. |
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| 288 | |||
| 289 | //EXID = 1:extended frame |
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| 290 | //RXBnSIDH = high standard ident (bit10->bit3 if standard, bit28->bit21 if ext) |
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| 291 | //RXBnSIDL(7:5) = low standard ident (bit2->bit0 if standard, bit20->bit18 if ext) |
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| 292 | //RXBnSIDL(1:0) = low standard ident (bit17->bit16 if ext) |
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| 293 | //RXBnEIDH = high extended ident (bit15->bit8) |
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| 294 | //RXBnEIDL = low extended ident (bit7->bit0) |
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| 295 | //RXBnDLC = Data length |
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| 296 | //RXBnDm = Data bytes. (0 <= m <= 7) |
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| 297 | |||
| 298 | // Same for Bn... (1 <= n <= 5) |
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| 299 | |||
| 300 | } |
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| 301 | |||
| 302 | |||
| 303 | /* |
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| 304 | * Function: canSendMessage |
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| 305 | * |
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| 306 | * Input: CAN_MESSAGE to send |
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| 307 | * Output: True if packet scheduled sucess, false otherwise. |
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| 308 | * Pre-conditions: canInit |
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| 309 | * Affects: .. |
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| 310 | * Depends: .. |
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| 311 | */ |
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| 312 | BOOL canSendMessage(CAN_MESSAGE cm) |
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| 313 | { |
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| 314 | BYTE defECANCON; |
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| 315 | |||
| 316 | // Save default ECANCON |
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| 317 | #ifdef CAN_ENCHANCED_MODE |
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| 318 | defECANCON=(ECANCON&0b00000)|0b10000; |
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| 319 | #else |
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| 320 | defECANCON=(CANCON&0b000)|0b100; |
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| 321 | #endif |
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| 322 | |||
| 323 | // Find the first empty transmitter. |
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| 324 | if ( TXB0CONbits.TXREQ == 0 ) |
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| 325 | { |
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| 326 | // TxBuffer0 is empty. Set EWIN bits to point to TXB0 |
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| 327 | #ifdef CAN_ENCHANCED_MODE |
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| 328 | ECANCON=(defECANCON&0b00000)|0b00011; |
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| 329 | #else |
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| 330 | //CANCON=(defECANCON&0b000)|0b100; |
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| 331 | #endif |
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| 332 | } |
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| 333 | else if ( TXB1CONbits.TXREQ == 0 ) |
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| 334 | { |
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| 335 | // TxBuffer1 is empty. Set EWIN bits to point to TXB1 |
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| 336 | #ifdef CAN_ENCHANCED_MODE |
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| 337 | ECANCON=(defECANCON&0b00000)|0b00100; |
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| 338 | #else |
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| 339 | //CANCON=(defECANCON&0b000)|0b011; |
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| 340 | #endif |
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| 341 | } |
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| 342 | else if ( TXB2CONbits.TXREQ == 0 ) |
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| 343 | { |
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| 344 | // TxBuffer2 is empty. Set EWIN bits to point to TXB2 |
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| 345 | #ifdef CAN_ENCHANCED_MODE |
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| 346 | ECANCON=(defECANCON&0b00000)|0b00101; |
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| 347 | #else |
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| 348 | //CANCON=(defECANCON&0b000)|0b010; |
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| 349 | #endif |
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| 350 | } |
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| 351 | // None of the transmit buffers were empty. |
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| 352 | else { return FALSE;} |
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| 353 | |||
| 354 | |||
| 355 | |||
| 356 | uartPutrs("Sending.."); |
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| 357 | |||
| 358 | // Set extended mode or not. |
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| 359 | TXB0SIDLbits.EXIDE=cm.extended; |
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| 360 | |||
| 361 | if (cm.extended==TRUE) |
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| 362 | { |
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| 363 | //Write extended ident. |
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| 364 | TXB0SIDH=(cm.ident[3]<3)+(cm.ident[2]>5); |
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| 365 | TXB0SIDL=(TXB0SIDL & 0b00011100)+((cm.ident[2] & 0b0001100)<3)+(cm.ident[2] & 0b00000011); |
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| 366 | TXB0EIDH=cm.ident[1]; |
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| 367 | TXB0EIDL=cm.ident[0]; |
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| 368 | } |
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| 369 | else |
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| 370 | { |
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| 371 | //Write standard ident. |
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| 372 | TXB0SIDH=(cm.ident[1]<5)+(cm.ident[0]>3); |
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| 373 | TXB0SIDL=(TXB0SIDL & 0b00011111)+(cm.ident[0]<5); |
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| 374 | } |
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| 375 | |||
| 376 | // Data length |
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| 377 | if (cm.data_length>8) TXB0DLC=8; else TXB0DLC=cm.data_length; |
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| 378 | |||
| 379 | // Data one bye one, for speed |
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| 380 | TXB0D0=cm.data[0]; TXB0D1=cm.data[1]; |
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| 381 | TXB0D2=cm.data[2]; TXB0D3=cm.data[3]; |
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| 382 | TXB0D4=cm.data[4]; TXB0D5=cm.data[5]; |
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| 383 | TXB0D6=cm.data[6]; TXB0D7=cm.data[7]; |
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| 384 | |||
| 385 | // mark as redy to transmit |
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| 386 | TXB0CONbits.TXREQ=1; |
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| 387 | |||
| 388 | uartPutrs("While"); |
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| 389 | while(TXB0CONbits.TXREQ); |
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| 390 | uartPutrs("after"); |
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| 391 | |||
| 392 | |||
| 393 | /* |
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| 394 | // Set extended mode or not. |
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| 395 | //RXB0SIDLbits.EXID=cm.extended; |
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| 396 | if (cm.extended==TRUE) |
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| 397 | { |
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| 398 | _asm |
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| 399 | bsf RXB0SIDL, 3, 0 |
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| 400 | _endasm |
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| 401 | } |
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| 402 | else |
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| 403 | { |
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| 404 | _asm |
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| 405 | bcf RXB0SIDL, 3, 0 |
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| 406 | _endasm |
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| 407 | } |
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| 408 | |||
| 409 | |||
| 410 | if (cm.extended==TRUE) |
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| 411 | { |
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| 412 | //Write extended ident. |
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| 413 | RXB0SIDH=(cm.ident[3]<3)+(cm.ident[2]>5); |
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| 414 | RXB0SIDL=(RXB0SIDL & 0b00011100)+((cm.ident[2] & 0b0001100)<3)+(cm.ident[2] & 0b00000011); |
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| 415 | RXB0EIDH=cm.ident[1]; |
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| 416 | RXB0EIDL=cm.ident[0]; |
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| 417 | } |
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| 418 | else |
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| 419 | { |
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| 420 | //Write standard ident. |
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| 421 | RXB0SIDH=(cm.ident[1]<5)+(cm.ident[0]>3); |
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| 422 | RXB0SIDL=(RXB0SIDL & 0b00011111)+(cm.ident[0]<5); |
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| 423 | } |
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| 424 | |||
| 425 | // Data length |
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| 426 | if (cm.data_length>8) RXB0DLC=8; else RXB0DLC=cm.data_length; |
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| 427 | |||
| 428 | // Data one bye one, for speed |
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| 429 | RXB0D0=cm.data[0]; RXB0D1=cm.data[1]; |
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| 430 | RXB0D2=cm.data[2]; RXB0D3=cm.data[3]; |
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| 431 | RXB0D4=cm.data[4]; RXB0D5=cm.data[5]; |
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| 432 | RXB0D6=cm.data[6]; RXB0D7=cm.data[7]; |
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| 433 | |||
| 434 | // mark as redy to transmit |
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| 435 | _asm |
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| 436 | bsf RXB0CON, 3, 0 |
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| 437 | _endasm |
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| 438 | |||
| 439 | // restore mapping |
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| 440 | #ifdef CAN_ENCHANCED_MODE |
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| 441 | ECANCON = defECANCON; |
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| 442 | #else |
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| 443 | CANCON = defECANCON; |
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| 444 | #endif |
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| 445 | */ |
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| 446 | |||
| 447 | |||
| 448 | |||
| 449 | |||
| 450 | return TRUE; |
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| 451 | |||
| 452 | } |
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| 453 | |||
| 454 | |||
| 455 | #endif //USE_CAN |