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  1. /*****************************************************************************
  2. *
  3. * File              TWI_Master.h compiled with gcc
  4. * Date              Dec 2, 2008
  5. * Source            Modified from AVR315 - TWI Master Implementation
  6. * Supported devices : All devices with a TWI module can be used.
  7. *                     The example is written for the ATmega168.
  8. *            Requires that clock be set at 4MHz.
  9. *
  10. * This is the hardware driver for the TWI module implementing the I2C bus.
  11. * 12/19/08  Added Random (memory) Read function.        -jkl
  12. * 5/3/09    Revised to allow Random Read with more than one address byte. Made buffer
  13. *               length 128 data bytes. -jkl
  14. *
  15. ****************************************************************************/
  16.  
  17. /****************************************************************************
  18.   TWI Status/Control register definitions
  19. ****************************************************************************/
  20. #define TWI_BUFFER_SIZE 131   // Slave Address + Memory start address (2 bytes) + 128 data bytes (message size)
  21.  
  22. // For 4MHz clock, data rate will be 100Kbps with 0x0C.
  23. // Using 0x0C and an 8MHz clock, data rate will be 200Kbps. If only 100Kbps is required,
  24. //  change this value t0 0x20.
  25. #define TWI_TWBR            0x0C        // TWI Bit rate Register setting.
  26.                                         // See Application note for detailed
  27.                                         // information on setting this value.
  28. // Not used defines!
  29. //#define TWI_TWPS          0x00        // This driver presumes prescaler = 00
  30.  
  31. /****************************************************************************
  32.   Global definitions
  33. ****************************************************************************/
  34.  
  35. union TWI_statusReg                       // Status byte holding flags.
  36. {
  37.     unsigned char all;
  38.     struct
  39.     {
  40.         unsigned char lastTransOK:1;
  41.         unsigned char memRead:1;
  42.         unsigned char unusedBits:6;
  43.     };
  44. };
  45.  
  46. extern union TWI_statusReg TWI_statusReg;
  47.  
  48. /****************************************************************************
  49.   Function definitions
  50. ****************************************************************************/
  51. void TWI_Master_Initialise( void );
  52. unsigned char TWI_Transceiver_Busy( void );
  53. unsigned char TWI_Get_State_Info( void );
  54. void TWI_Start_Random_Read( unsigned char * , unsigned char, unsigned char );
  55. void TWI_Start_Read_Write( unsigned char * , unsigned char );
  56. unsigned char TWI_Read_Data_From_Buffer( unsigned char *, unsigned char );
  57.  
  58. /****************************************************************************
  59.   Bit and byte definitions
  60. ****************************************************************************/
  61. #define TWI_READ_BIT  0       // Bit position for R/W bit in "address byte".
  62. #define TWI_ADR_BITS  1       // Bit position for LSB of the slave address bits in the init byte.
  63.  
  64. #define TRUE          1
  65. #define FALSE         0
  66.  
  67. /****************************************************************************
  68.   TWI State codes
  69.   Note: 3 lsbs are for prescale value and should be masked out. (12/2 -jkl)
  70. ****************************************************************************/
  71. // General TWI Master staus codes                      
  72. #define TWI_START                  0x08  // START has been transmitted  
  73. #define TWI_REP_START              0x10  // Repeated START has been transmitted
  74. #define TWI_ARB_LOST               0x38  // Arbitration lost
  75.  
  76. // TWI Master Transmitter staus codes                      
  77. #define TWI_MTX_ADR_ACK            0x18  // SLA+W has been tramsmitted and ACK received
  78. #define TWI_MTX_ADR_NACK           0x20  // SLA+W has been tramsmitted and NACK received
  79. #define TWI_MTX_DATA_ACK           0x28  // Data byte has been tramsmitted and ACK received
  80. #define TWI_MTX_DATA_NACK          0x30  // Data byte has been tramsmitted and NACK received
  81.  
  82. // TWI Master Receiver staus codes  
  83. #define TWI_MRX_ADR_ACK            0x40  // SLA+R has been tramsmitted and ACK received
  84. #define TWI_MRX_ADR_NACK           0x48  // SLA+R has been tramsmitted and NACK received
  85. #define TWI_MRX_DATA_ACK           0x50  // Data byte has been received and ACK tramsmitted
  86. #define TWI_MRX_DATA_NACK          0x58  // Data byte has been received and NACK tramsmitted
  87.  
  88. // TWI Miscellaneous status codes
  89. #define TWI_NO_STATE               0xF8  // No relevant state information available; TWINT = �0�
  90. #define TWI_BUS_ERROR              0x00  // Bus error due to an illegal START or STOP condition
  91.  
  92.