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  1. /*****************************************************************************
  2. * vim:sw=8:ts=8:si:et
  3. *
  4. * Title        : Microchip ENC28J60 Ethernet Interface Driver
  5. * Author        : Pascal Stang (c)2005
  6. * Modified by Guido Socher
  7. * Copyright: GPL V2
  8. *
  9. *This driver provides initialization and transmit/receive
  10. *functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.
  11. *This chip is novel in that it is a full MAC+PHY interface all in a 28-pin
  12. *chip, using an SPI interface to the host processor.
  13. *
  14. *
  15. *****************************************************************************/
  16. //@{
  17.  
  18.  
  19. #ifndef ENC28J60_H
  20. #define ENC28J60_H
  21. #include <inttypes.h>
  22.  
  23. // ENC28J60 Control Registers
  24. // Control register definitions are a combination of address,
  25. // bank number, and Ethernet/MAC/PHY indicator bits.
  26. // - Register address        (bits 0-4)
  27. // - Bank number        (bits 5-6)
  28. // - MAC/PHY indicator        (bit 7)
  29. #define ADDR_MASK        0x1F
  30. #define BANK_MASK        0x60
  31. #define SPRD_MASK        0x80
  32. // All-bank registers
  33. #define EIE              0x1B
  34. #define EIR              0x1C
  35. #define ESTAT            0x1D
  36. #define ECON2            0x1E
  37. #define ECON1            0x1F
  38. // Bank 0 registers
  39. #define ERDPTL           (0x00|0x00)
  40. #define ERDPTH           (0x01|0x00)
  41. #define EWRPTL           (0x02|0x00)
  42. #define EWRPTH           (0x03|0x00)
  43. #define ETXSTL           (0x04|0x00)
  44. #define ETXSTH           (0x05|0x00)
  45. #define ETXNDL           (0x06|0x00)
  46. #define ETXNDH           (0x07|0x00)
  47. #define ERXSTL           (0x08|0x00)
  48. #define ERXSTH           (0x09|0x00)
  49. #define ERXNDL           (0x0A|0x00)
  50. #define ERXNDH           (0x0B|0x00)
  51. #define ERXRDPTL         (0x0C|0x00)
  52. #define ERXRDPTH         (0x0D|0x00)
  53. #define ERXWRPTL         (0x0E|0x00)
  54. #define ERXWRPTH         (0x0F|0x00)
  55. #define EDMASTL          (0x10|0x00)
  56. #define EDMASTH          (0x11|0x00)
  57. #define EDMANDL          (0x12|0x00)
  58. #define EDMANDH          (0x13|0x00)
  59. #define EDMADSTL         (0x14|0x00)
  60. #define EDMADSTH         (0x15|0x00)
  61. #define EDMACSL          (0x16|0x00)
  62. #define EDMACSH          (0x17|0x00)
  63. // Bank 1 registers
  64. #define EHT0             (0x00|0x20)
  65. #define EHT1             (0x01|0x20)
  66. #define EHT2             (0x02|0x20)
  67. #define EHT3             (0x03|0x20)
  68. #define EHT4             (0x04|0x20)
  69. #define EHT5             (0x05|0x20)
  70. #define EHT6             (0x06|0x20)
  71. #define EHT7             (0x07|0x20)
  72. #define EPMM0            (0x08|0x20)
  73. #define EPMM1            (0x09|0x20)
  74. #define EPMM2            (0x0A|0x20)
  75. #define EPMM3            (0x0B|0x20)
  76. #define EPMM4            (0x0C|0x20)
  77. #define EPMM5            (0x0D|0x20)
  78. #define EPMM6            (0x0E|0x20)
  79. #define EPMM7            (0x0F|0x20)
  80. #define EPMCSL           (0x10|0x20)
  81. #define EPMCSH           (0x11|0x20)
  82. #define EPMOL            (0x14|0x20)
  83. #define EPMOH            (0x15|0x20)
  84. #define EWOLIE           (0x16|0x20)
  85. #define EWOLIR           (0x17|0x20)
  86. #define ERXFCON          (0x18|0x20)
  87. #define EPKTCNT          (0x19|0x20)
  88. // Bank 2 registers
  89. #define MACON1           (0x00|0x40|0x80)
  90. #define MACON2           (0x01|0x40|0x80)
  91. #define MACON3           (0x02|0x40|0x80)
  92. #define MACON4           (0x03|0x40|0x80)
  93. #define MABBIPG          (0x04|0x40|0x80)
  94. #define MAIPGL           (0x06|0x40|0x80)
  95. #define MAIPGH           (0x07|0x40|0x80)
  96. #define MACLCON1         (0x08|0x40|0x80)
  97. #define MACLCON2         (0x09|0x40|0x80)
  98. #define MAMXFLL          (0x0A|0x40|0x80)
  99. #define MAMXFLH          (0x0B|0x40|0x80)
  100. #define MAPHSUP          (0x0D|0x40|0x80)
  101. #define MICON            (0x11|0x40|0x80)
  102. #define MICMD            (0x12|0x40|0x80)
  103. #define MIREGADR         (0x14|0x40|0x80)
  104. #define MIWRL            (0x16|0x40|0x80)
  105. #define MIWRH            (0x17|0x40|0x80)
  106. #define MIRDL            (0x18|0x40|0x80)
  107. #define MIRDH            (0x19|0x40|0x80)
  108. // Bank 3 registers
  109. #define MAADR1           (0x00|0x60|0x80)
  110. #define MAADR0           (0x01|0x60|0x80)
  111. #define MAADR3           (0x02|0x60|0x80)
  112. #define MAADR2           (0x03|0x60|0x80)
  113. #define MAADR5           (0x04|0x60|0x80)
  114. #define MAADR4           (0x05|0x60|0x80)
  115. #define EBSTSD           (0x06|0x60)
  116. #define EBSTCON          (0x07|0x60)
  117. #define EBSTCSL          (0x08|0x60)
  118. #define EBSTCSH          (0x09|0x60)
  119. #define MISTAT           (0x0A|0x60|0x80)
  120. #define EREVID           (0x12|0x60)
  121. #define ECOCON           (0x15|0x60)
  122. #define EFLOCON          (0x17|0x60)
  123. #define EPAUSL           (0x18|0x60)
  124. #define EPAUSH           (0x19|0x60)
  125. // PHY registers
  126. #define PHCON1           0x00
  127. #define PHSTAT1          0x01
  128. #define PHHID1           0x02
  129. #define PHHID2           0x03
  130. #define PHCON2           0x10
  131. #define PHSTAT2          0x11
  132. #define PHIE             0x12
  133. #define PHIR             0x13
  134. #define PHLCON           0x14
  135.  
  136. // ENC28J60 ERXFCON Register Bit Definitions
  137. #define ERXFCON_UCEN     0x80
  138. #define ERXFCON_ANDOR    0x40
  139. #define ERXFCON_CRCEN    0x20
  140. #define ERXFCON_PMEN     0x10
  141. #define ERXFCON_MPEN     0x08
  142. #define ERXFCON_HTEN     0x04
  143. #define ERXFCON_MCEN     0x02
  144. #define ERXFCON_BCEN     0x01
  145. // ENC28J60 EIE Register Bit Definitions
  146. #define EIE_INTIE        0x80
  147. #define EIE_PKTIE        0x40
  148. #define EIE_DMAIE        0x20
  149. #define EIE_LINKIE       0x10
  150. #define EIE_TXIE         0x08
  151. #define EIE_WOLIE        0x04
  152. #define EIE_TXERIE       0x02
  153. #define EIE_RXERIE       0x01
  154. // ENC28J60 EIR Register Bit Definitions
  155. #define EIR_PKTIF        0x40
  156. #define EIR_DMAIF        0x20
  157. #define EIR_LINKIF       0x10
  158. #define EIR_TXIF         0x08
  159. #define EIR_WOLIF        0x04
  160. #define EIR_TXERIF       0x02
  161. #define EIR_RXERIF       0x01
  162. // ENC28J60 ESTAT Register Bit Definitions
  163. #define ESTAT_INT        0x80
  164. #define ESTAT_LATECOL    0x10
  165. #define ESTAT_RXBUSY     0x04
  166. #define ESTAT_TXABRT     0x02
  167. #define ESTAT_CLKRDY     0x01
  168. // ENC28J60 ECON2 Register Bit Definitions
  169. #define ECON2_AUTOINC    0x80
  170. #define ECON2_PKTDEC     0x40
  171. #define ECON2_PWRSV      0x20
  172. #define ECON2_VRPS       0x08
  173. // ENC28J60 ECON1 Register Bit Definitions
  174. #define ECON1_TXRST      0x80
  175. #define ECON1_RXRST      0x40
  176. #define ECON1_DMAST      0x20
  177. #define ECON1_CSUMEN     0x10
  178. #define ECON1_TXRTS      0x08
  179. #define ECON1_RXEN       0x04
  180. #define ECON1_BSEL1      0x02
  181. #define ECON1_BSEL0      0x01
  182. // ENC28J60 MACON1 Register Bit Definitions
  183. #define MACON1_LOOPBK    0x10
  184. #define MACON1_TXPAUS    0x08
  185. #define MACON1_RXPAUS    0x04
  186. #define MACON1_PASSALL   0x02
  187. #define MACON1_MARXEN    0x01
  188. // ENC28J60 MACON2 Register Bit Definitions
  189. #define MACON2_MARST     0x80
  190. #define MACON2_RNDRST    0x40
  191. #define MACON2_MARXRST   0x08
  192. #define MACON2_RFUNRST   0x04
  193. #define MACON2_MATXRST   0x02
  194. #define MACON2_TFUNRST   0x01
  195. // ENC28J60 MACON3 Register Bit Definitions
  196. #define MACON3_PADCFG2   0x80
  197. #define MACON3_PADCFG1   0x40
  198. #define MACON3_PADCFG0   0x20
  199. #define MACON3_TXCRCEN   0x10
  200. #define MACON3_PHDRLEN   0x08
  201. #define MACON3_HFRMLEN   0x04
  202. #define MACON3_FRMLNEN   0x02
  203. #define MACON3_FULDPX    0x01
  204. // ENC28J60 MICMD Register Bit Definitions
  205. #define MICMD_MIISCAN    0x02
  206. #define MICMD_MIIRD      0x01
  207. // ENC28J60 MISTAT Register Bit Definitions
  208. #define MISTAT_NVALID    0x04
  209. #define MISTAT_SCAN      0x02
  210. #define MISTAT_BUSY      0x01
  211. // ENC28J60 PHY PHCON1 Register Bit Definitions
  212. #define PHCON1_PRST      0x8000
  213. #define PHCON1_PLOOPBK   0x4000
  214. #define PHCON1_PPWRSV    0x0800
  215. #define PHCON1_PDPXMD    0x0100
  216. // ENC28J60 PHY PHSTAT1 Register Bit Definitions
  217. #define PHSTAT1_PFDPX    0x1000
  218. #define PHSTAT1_PHDPX    0x0800
  219. #define PHSTAT1_LLSTAT   0x0004
  220. #define PHSTAT1_JBSTAT   0x0002
  221. // ENC28J60 PHY PHCON2 Register Bit Definitions
  222. #define PHCON2_FRCLINK   0x4000
  223. #define PHCON2_TXDIS     0x2000
  224. #define PHCON2_JABBER    0x0400
  225. #define PHCON2_HDLDIS    0x0100
  226.  
  227. // ENC28J60 Packet Control Byte Bit Definitions
  228. #define PKTCTRL_PHUGEEN  0x08
  229. #define PKTCTRL_PPADEN   0x04
  230. #define PKTCTRL_PCRCEN   0x02
  231. #define PKTCTRL_POVERRIDE 0x01
  232.  
  233. // SPI operation codes
  234. #define ENC28J60_READ_CTRL_REG       0x00
  235. #define ENC28J60_READ_BUF_MEM        0x3A
  236. #define ENC28J60_WRITE_CTRL_REG      0x40
  237. #define ENC28J60_WRITE_BUF_MEM       0x7A
  238. #define ENC28J60_BIT_FIELD_SET       0x80
  239. #define ENC28J60_BIT_FIELD_CLR       0xA0
  240. #define ENC28J60_SOFT_RESET          0xFF
  241.  
  242.  
  243. // The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
  244. // buffer boundaries applied to internal 8K ram
  245. // the entire available packet buffer space is allocated
  246. //
  247. // start with recbuf at 0/
  248. #define RXSTART_INIT     0x0
  249. // receive buffer end
  250. #define RXSTOP_INIT      (0x1FFF-0x0600-1)
  251. // start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
  252. #define TXSTART_INIT     (0x1FFF-0x0600)
  253. // stp TX buffer at end of mem
  254. #define TXSTOP_INIT      0x1FFF
  255. //
  256. // max frame length which the conroller will accept:
  257. #define        MAX_FRAMELEN        1500        // (note: maximum ethernet frame length would be 1518)
  258. //#define MAX_FRAMELEN     600
  259.  
  260.  
  261. // functions
  262. extern uint8_t enc28j60ReadOp(uint8_t op, uint8_t address);
  263. extern void enc28j60WriteOp(uint8_t op, uint8_t address, uint8_t data);
  264. extern void enc28j60ReadBuffer(uint16_t len, uint8_t* data);
  265. extern void enc28j60WriteBuffer(uint16_t len, uint8_t* data);
  266. extern void enc28j60SetBank(uint8_t address);
  267. extern uint8_t enc28j60Read(uint8_t address);
  268. extern void enc28j60Write(uint8_t address, uint8_t data);
  269. extern void enc28j60PhyWrite(uint8_t address, uint16_t data);
  270. extern void enc28j60Init(uint8_t* macaddr);
  271. extern void enc28j60PacketSend(uint16_t len, uint8_t* packet);
  272. extern uint16_t enc28j60PacketReceive(uint16_t maxlen, uint8_t* packet);
  273. extern uint8_t enc28j60getrev(void);
  274.  
  275. #endif
  276. //@}
  277.