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| - | 1 | #ifndef TWI_MASTER_H |
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| - | 2 | #define TWI_MASTER_H |
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| - | 3 | ||
| 1 | /***************************************************************************** |
4 | /***************************************************************************** |
| 2 | * |
5 | * |
| 3 | * File TWI_Master.h compiled with gcc |
6 | * File TWI_Master.h compiled with gcc |
| 4 | * Date Dec 2, 2008 |
7 | * Date Dec 2, 2008 |
| 5 | * Source Modified from AVR315 - TWI Master Implementation |
8 | * Source Modified from AVR315 - TWI Master Implementation |
| Line 52... | Line 55... | ||
| 52 | unsigned char TWI_Transceiver_Busy( void ); |
55 | unsigned char TWI_Transceiver_Busy( void ); |
| 53 | unsigned char TWI_Get_State_Info( void ); |
56 | unsigned char TWI_Get_State_Info( void ); |
| 54 | void TWI_Start_Random_Read( unsigned char * , unsigned char, unsigned char ); |
57 | void TWI_Start_Random_Read( unsigned char * , unsigned char, unsigned char ); |
| 55 | void TWI_Start_Read_Write( unsigned char * , unsigned char ); |
58 | void TWI_Start_Read_Write( unsigned char * , unsigned char ); |
| 56 | unsigned char TWI_Read_Data_From_Buffer( unsigned char *, unsigned char ); |
59 | unsigned char TWI_Read_Data_From_Buffer( unsigned char *, unsigned char ); |
| 57 | 60 | ||
| 58 | /**************************************************************************** |
61 | /**************************************************************************** |
| 59 | Bit and byte definitions |
62 | Bit and byte definitions |
| 60 | ****************************************************************************/ |
63 | ****************************************************************************/ |
| 61 | #define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte". |
64 | #define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte". |
| 62 | #define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte. |
65 | #define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte. |
| Line 86... | Line 89... | ||
| 86 | #define TWI_MRX_DATA_NACK 0x58 // Data byte has been received and NACK tramsmitted |
89 | #define TWI_MRX_DATA_NACK 0x58 // Data byte has been received and NACK tramsmitted |
| 87 | 90 | ||
| 88 | // TWI Miscellaneous status codes |
91 | // TWI Miscellaneous status codes |
| 89 | #define TWI_NO_STATE 0xF8 // No relevant state information available; TWINT = �0� |
92 | #define TWI_NO_STATE 0xF8 // No relevant state information available; TWINT = �0� |
| 90 | #define TWI_BUS_ERROR 0x00 // Bus error due to an illegal START or STOP condition |
93 | #define TWI_BUS_ERROR 0x00 // Bus error due to an illegal START or STOP condition |
| 91 | - | ||
| - | 94 | #endif /* TWI_MASTER_H */ |
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