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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 361 | andfri | 1 | /************************************************************************* |
| 2 | Title: Interrupt UART library with receive/transmit circular buffers |
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| 3 | Author: Peter Fleury <pfleury@gmx.ch> http://jump.to/fleury |
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| 4 | File: $Id: uart.c,v 1.5.2.10 2005/11/15 19:49:12 peter Exp $ |
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| 5 | Software: AVR-GCC 3.3 |
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| 6 | Hardware: any AVR with built-in UART, |
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| 7 | tested on AT90S8515 at 4 Mhz and ATmega at 1Mhz |
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| 8 | |||
| 9 | DESCRIPTION: |
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| 10 | An interrupt is generated when the UART has finished transmitting or |
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| 11 | receiving a byte. The interrupt handling routines use circular buffers |
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| 12 | for buffering received and transmitted data. |
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| 13 | |||
| 14 | The UART_RX_BUFFER_SIZE and UART_TX_BUFFER_SIZE variables define |
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| 15 | the buffer size in bytes. Note that these variables must be a |
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| 16 | power of 2. |
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| 17 | |||
| 18 | USAGE: |
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| 19 | Refere to the header file uart.h for a description of the routines. |
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| 20 | See also example test_uart.c. |
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| 21 | |||
| 22 | NOTES: |
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| 23 | Based on Atmel Application Note AVR306 |
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| 24 | |||
| 25 | *************************************************************************/ |
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| 26 | #include <avr/io.h> |
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| 27 | #include <avr/interrupt.h> |
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| 28 | #include <avr/pgmspace.h> |
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| 29 | #include <drivers/uart/uart.h> |
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| 30 | |||
| 31 | |||
| 32 | /* |
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| 33 | * constants and macros |
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| 34 | */ |
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| 35 | |||
| 36 | /* size of RX/TX buffers */ |
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| 37 | #define UART_RX_BUFFER_MASK ( UART_RX_BUFFER_SIZE - 1) |
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| 38 | #define UART_TX_BUFFER_MASK ( UART_TX_BUFFER_SIZE - 1) |
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| 39 | |||
| 40 | #if ( UART_RX_BUFFER_SIZE & UART_RX_BUFFER_MASK ) |
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| 41 | #error RX buffer size is not a power of 2 |
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| 42 | #endif |
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| 43 | #if ( UART_TX_BUFFER_SIZE & UART_TX_BUFFER_MASK ) |
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| 44 | #error TX buffer size is not a power of 2 |
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| 45 | #endif |
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| 46 | |||
| 47 | #if defined(__AVR_AT90S2313__) \ |
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| 48 | || defined(__AVR_AT90S4414__) || defined(__AVR_AT90S4434__) \ |
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| 49 | || defined(__AVR_AT90S8515__) || defined(__AVR_AT90S8535__) \ |
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| 50 | || defined(__AVR_ATmega103__) |
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| 51 | /* old AVR classic or ATmega103 with one UART */ |
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| 52 | #define AT90_UART |
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| 53 | #define UART0_RECEIVE_INTERRUPT SIG_UART_RECV |
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| 54 | #define UART0_TRANSMIT_INTERRUPT SIG_UART_DATA |
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| 55 | #define UART0_STATUS USR |
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| 56 | #define UART0_CONTROL UCR |
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| 57 | #define UART0_DATA UDR |
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| 58 | #define UART0_UDRIE UDRIE |
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| 59 | #elif defined(__AVR_AT90S2333__) || defined(__AVR_AT90S4433__) |
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| 60 | /* old AVR classic with one UART */ |
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| 61 | #define AT90_UART |
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| 62 | #define UART0_RECEIVE_INTERRUPT SIG_UART_RECV |
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| 63 | #define UART0_TRANSMIT_INTERRUPT SIG_UART_DATA |
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| 64 | #define UART0_STATUS UCSRA |
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| 65 | #define UART0_CONTROL UCSRB |
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| 66 | #define UART0_DATA UDR |
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| 67 | #define UART0_UDRIE UDRIE |
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| 68 | #elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega16__) || defined(__AVR_ATmega32__) \ |
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| 69 | || defined(__AVR_ATmega8515__) || defined(__AVR_ATmega8535__) \ |
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| 70 | || defined(__AVR_ATmega323__) |
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| 71 | /* ATmega with one USART */ |
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| 72 | #define ATMEGA_USART |
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| 73 | #define UART0_RECEIVE_INTERRUPT SIG_UART_RECV |
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| 74 | #define UART0_TRANSMIT_INTERRUPT SIG_UART_DATA |
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| 75 | #define UART0_STATUS UCSRA |
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| 76 | #define UART0_CONTROL UCSRB |
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| 77 | #define UART0_DATA UDR |
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| 78 | #define UART0_UDRIE UDRIE |
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| 79 | #elif defined(__AVR_ATmega163__) |
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| 80 | /* ATmega163 with one UART */ |
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| 81 | #define ATMEGA_UART |
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| 82 | #define UART0_RECEIVE_INTERRUPT SIG_UART_RECV |
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| 83 | #define UART0_TRANSMIT_INTERRUPT SIG_UART_DATA |
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| 84 | #define UART0_STATUS UCSRA |
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| 85 | #define UART0_CONTROL UCSRB |
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| 86 | #define UART0_DATA UDR |
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| 87 | #define UART0_UDRIE UDRIE |
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| 88 | #elif defined(__AVR_ATmega162__) |
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| 89 | /* ATmega with two USART */ |
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| 90 | #define ATMEGA_USART0 |
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| 91 | #define ATMEGA_USART1 |
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| 92 | #define UART0_RECEIVE_INTERRUPT SIG_USART0_RECV |
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| 93 | #define UART1_RECEIVE_INTERRUPT SIG_USART1_RECV |
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| 94 | #define UART0_TRANSMIT_INTERRUPT SIG_USART0_DATA |
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| 95 | #define UART1_TRANSMIT_INTERRUPT SIG_USART1_DATA |
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| 96 | #define UART0_STATUS UCSR0A |
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| 97 | #define UART0_CONTROL UCSR0B |
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| 98 | #define UART0_DATA UDR0 |
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| 99 | #define UART0_UDRIE UDRIE0 |
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| 100 | #define UART1_STATUS UCSR1A |
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| 101 | #define UART1_CONTROL UCSR1B |
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| 102 | #define UART1_DATA UDR1 |
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| 103 | #define UART1_UDRIE UDRIE1 |
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| 104 | #elif defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__) |
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| 105 | /* ATmega with two USART */ |
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| 106 | #define ATMEGA_USART0 |
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| 107 | #define ATMEGA_USART1 |
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| 108 | #define UART0_RECEIVE_INTERRUPT SIG_UART0_RECV |
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| 109 | #define UART1_RECEIVE_INTERRUPT SIG_UART1_RECV |
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| 110 | #define UART0_TRANSMIT_INTERRUPT SIG_UART0_DATA |
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| 111 | #define UART1_TRANSMIT_INTERRUPT SIG_UART1_DATA |
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| 112 | #define UART0_STATUS UCSR0A |
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| 113 | #define UART0_CONTROL UCSR0B |
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| 114 | #define UART0_DATA UDR0 |
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| 115 | #define UART0_UDRIE UDRIE0 |
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| 116 | #define UART1_STATUS UCSR1A |
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| 117 | #define UART1_CONTROL UCSR1B |
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| 118 | #define UART1_DATA UDR1 |
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| 119 | #define UART1_UDRIE UDRIE1 |
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| 120 | #elif defined(__AVR_ATmega161__) |
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| 121 | /* ATmega with UART */ |
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| 122 | #error "AVR ATmega161 currently not supported by this libaray !" |
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| 123 | #elif defined(__AVR_ATmega169__) |
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| 124 | /* ATmega with one USART */ |
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| 125 | #define ATMEGA_USART |
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| 126 | #define UART0_RECEIVE_INTERRUPT SIG_USART_RECV |
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| 127 | #define UART0_TRANSMIT_INTERRUPT SIG_USART_DATA |
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| 128 | #define UART0_STATUS UCSRA |
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| 129 | #define UART0_CONTROL UCSRB |
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| 130 | #define UART0_DATA UDR |
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| 131 | #define UART0_UDRIE UDRIE |
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| 1468 | arune | 132 | #elif defined(__AVR_ATmega48__) ||defined(__AVR_ATmega88__) || defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__) |
| 361 | andfri | 133 | #define ATMEGA_USART0 |
| 1695 | arune | 134 | #define UART0_RECEIVE_INTERRUPT USART_RX_vect |
| 135 | #define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect |
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| 361 | andfri | 136 | #define UART0_STATUS UCSR0A |
| 137 | #define UART0_CONTROL UCSR0B |
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| 138 | #define UART0_DATA UDR0 |
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| 139 | #define UART0_UDRIE UDRIE0 |
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| 140 | #elif defined(__AVR_ATtiny2313__) |
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| 141 | #define ATMEGA_USART |
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| 142 | #define UART0_RECEIVE_INTERRUPT SIG_USART0_RX |
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| 143 | #define UART0_TRANSMIT_INTERRUPT SIG_USART0_UDRE |
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| 144 | #define UART0_STATUS UCSRA |
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| 145 | #define UART0_CONTROL UCSRB |
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| 146 | #define UART0_DATA UDR |
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| 147 | #define UART0_UDRIE UDRIE |
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| 148 | #else |
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| 149 | #error "no UART definition for MCU available" |
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| 150 | #endif |
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| 151 | |||
| 152 | |||
| 153 | /* |
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| 154 | * module global variables |
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| 155 | */ |
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| 156 | static volatile unsigned char UART_TxBuf[UART_TX_BUFFER_SIZE]; |
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| 157 | static volatile unsigned char UART_RxBuf[UART_RX_BUFFER_SIZE]; |
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| 158 | static volatile unsigned char UART_TxHead; |
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| 159 | static volatile unsigned char UART_TxTail; |
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| 160 | static volatile unsigned char UART_RxHead; |
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| 161 | static volatile unsigned char UART_RxTail; |
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| 162 | static volatile unsigned char UART_LastRxError; |
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| 163 | |||
| 164 | #if defined( ATMEGA_USART1 ) |
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| 165 | static volatile unsigned char UART1_TxBuf[UART_TX_BUFFER_SIZE]; |
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| 166 | static volatile unsigned char UART1_RxBuf[UART_RX_BUFFER_SIZE]; |
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| 167 | static volatile unsigned char UART1_TxHead; |
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| 168 | static volatile unsigned char UART1_TxTail; |
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| 169 | static volatile unsigned char UART1_RxHead; |
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| 170 | static volatile unsigned char UART1_RxTail; |
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| 171 | static volatile unsigned char UART1_LastRxError; |
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| 172 | #endif |
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| 173 | |||
| 174 | |||
| 1576 | myhrman | 175 | static uint8_t parityEnabled = 0; |
| 176 | static uint8_t parityOdd = 0; |
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| 177 | static uint8_t twoStopBits = 0; |
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| 178 | static uint8_t charSize = 8; |
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| 361 | andfri | 179 | |
| 1576 | myhrman | 180 | |
| 1578 | arune | 181 | static void uart_updateConfig(void) |
| 1576 | myhrman | 182 | { |
| 183 | uint8_t CHARSIZE_MASK = 0; |
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| 1578 | arune | 184 | if (charSize==5) { |
| 185 | CHARSIZE_MASK = (0<<UCSZ02) | (0<<UCSZ01) | (0<<UCSZ00); |
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| 1576 | myhrman | 186 | } |
| 1578 | arune | 187 | else if (charSize==6) { |
| 188 | CHARSIZE_MASK = (0<<UCSZ02) | (0<<UCSZ01) | (1<<UCSZ00); |
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| 1576 | myhrman | 189 | } |
| 1578 | arune | 190 | else if (charSize==7) { |
| 191 | CHARSIZE_MASK = (0<<UCSZ02) | (1<<UCSZ01) | (0<<UCSZ00); |
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| 1576 | myhrman | 192 | } |
| 1578 | arune | 193 | else if (charSize==8) { |
| 194 | CHARSIZE_MASK = (0<<UCSZ02) | (1<<UCSZ01) | (1<<UCSZ00); |
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| 1576 | myhrman | 195 | } |
| 1578 | arune | 196 | else if (charSize==9) { |
| 197 | CHARSIZE_MASK = (1<<UCSZ02) | (1<<UCSZ01) | (1<<UCSZ00); |
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| 1576 | myhrman | 198 | } |
| 1738 | myhrman | 199 | UCSR0C = (parityEnabled<<UPM01) | (parityOdd<<UPM00) | (twoStopBits<<USBS0) | CHARSIZE_MASK; |
| 1576 | myhrman | 200 | } |
| 201 | |||
| 202 | |||
| 203 | void uart_setParity(uint8_t enabled, uint8_t odd) |
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| 204 | { |
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| 205 | parityEnabled = enabled; |
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| 206 | parityOdd = odd; |
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| 207 | uart_updateConfig(); |
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| 208 | } |
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| 209 | |||
| 210 | |||
| 211 | void uart_setStopbits(uint8_t nrStopbits) |
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| 212 | { |
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| 213 | twoStopBits = (nrStopbits == 2) ? 1 : 0; |
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| 214 | uart_updateConfig(); |
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| 215 | } |
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| 216 | |||
| 217 | |||
| 218 | void uart_setDatabits(uint8_t nrDatabits) |
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| 219 | { |
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| 220 | if (nrDatabits >=5 && nrDatabits <=9) { |
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| 221 | charSize = nrDatabits; |
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| 222 | } |
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| 223 | uart_updateConfig(); |
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| 224 | } |
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| 225 | |||
| 226 | |||
| 1695 | arune | 227 | ISR(UART0_RECEIVE_INTERRUPT) |
| 361 | andfri | 228 | /************************************************************************* |
| 229 | Function: UART Receive Complete interrupt |
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| 230 | Purpose: called when the UART has received a character |
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| 231 | **************************************************************************/ |
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| 232 | { |
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| 233 | unsigned char tmphead; |
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| 234 | unsigned char data; |
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| 235 | unsigned char usr; |
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| 236 | unsigned char lastRxError; |
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| 237 | |||
| 238 | |||
| 239 | /* read UART status register and UART data register */ |
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| 240 | usr = UART0_STATUS; |
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| 241 | data = UART0_DATA; |
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| 242 | |||
| 243 | /* */ |
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| 244 | #if defined( AT90_UART ) |
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| 245 | lastRxError = (usr & (_BV(FE)|_BV(DOR)) ); |
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| 246 | #elif defined( ATMEGA_USART ) |
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| 247 | lastRxError = (usr & (_BV(FE)|_BV(DOR)) ); |
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| 248 | #elif defined( ATMEGA_USART0 ) |
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| 249 | lastRxError = (usr & (_BV(FE0)|_BV(DOR0)) ); |
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| 250 | #elif defined ( ATMEGA_UART ) |
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| 251 | lastRxError = (usr & (_BV(FE)|_BV(DOR)) ); |
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| 252 | #endif |
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| 253 | |||
| 254 | /* calculate buffer index */ |
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| 255 | tmphead = ( UART_RxHead + 1) & UART_RX_BUFFER_MASK; |
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| 256 | |||
| 257 | if ( tmphead == UART_RxTail ) { |
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| 258 | /* error: receive buffer overflow */ |
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| 259 | lastRxError = UART_BUFFER_OVERFLOW >> 8; |
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| 260 | }else{ |
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| 261 | /* store new index */ |
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| 262 | UART_RxHead = tmphead; |
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| 263 | /* store received data in buffer */ |
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| 264 | UART_RxBuf[tmphead] = data; |
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| 265 | } |
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| 266 | UART_LastRxError = lastRxError; |
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| 267 | } |
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| 268 | |||
| 269 | |||
| 1695 | arune | 270 | ISR(UART0_TRANSMIT_INTERRUPT) |
| 361 | andfri | 271 | /************************************************************************* |
| 272 | Function: UART Data Register Empty interrupt |
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| 273 | Purpose: called when the UART is ready to transmit the next byte |
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| 274 | **************************************************************************/ |
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| 275 | { |
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| 276 | unsigned char tmptail; |
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| 277 | |||
| 278 | |||
| 279 | if ( UART_TxHead != UART_TxTail) { |
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| 280 | /* calculate and store new buffer index */ |
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| 281 | tmptail = (UART_TxTail + 1) & UART_TX_BUFFER_MASK; |
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| 282 | UART_TxTail = tmptail; |
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| 283 | /* get one byte from buffer and write it to UART */ |
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| 284 | UART0_DATA = UART_TxBuf[tmptail]; /* start transmission */ |
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| 285 | }else{ |
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| 286 | /* tx buffer empty, disable UDRE interrupt */ |
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| 287 | UART0_CONTROL &= ~_BV(UART0_UDRIE); |
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| 288 | } |
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| 289 | } |
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| 290 | |||
| 291 | |||
| 292 | /************************************************************************* |
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| 293 | Function: uart_init() |
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| 294 | Purpose: initialize UART and set baudrate |
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| 295 | Input: baudrate using macro UART_BAUD_SELECT() |
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| 296 | Returns: none |
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| 297 | **************************************************************************/ |
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| 298 | void uart_init(unsigned int baudrate) |
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| 299 | { |
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| 300 | UART_TxHead = 0; |
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| 301 | UART_TxTail = 0; |
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| 302 | UART_RxHead = 0; |
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| 303 | UART_RxTail = 0; |
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| 304 | |||
| 305 | #if defined( AT90_UART ) |
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| 306 | /* set baud rate */ |
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| 307 | UBRR = (unsigned char)baudrate; |
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| 308 | |||
| 309 | /* enable UART receiver and transmmitter and receive complete interrupt */ |
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| 310 | UART0_CONTROL = _BV(RXCIE)|_BV(RXEN)|_BV(TXEN); |
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| 311 | |||
| 312 | #elif defined (ATMEGA_USART) |
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| 313 | /* Set baud rate */ |
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| 314 | if ( baudrate & 0x8000 ) |
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| 315 | { |
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| 316 | UART0_STATUS = (1<<U2X); //Enable 2x speed |
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| 317 | baudrate &= ~0x8000; |
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| 318 | } |
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| 319 | UBRRH = (unsigned char)(baudrate>>8); |
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| 320 | UBRRL = (unsigned char) baudrate; |
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| 321 | |||
| 322 | /* Enable USART receiver and transmitter and receive complete interrupt */ |
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| 323 | UART0_CONTROL = _BV(RXCIE)|(1<<RXEN)|(1<<TXEN); |
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| 324 | |||
| 325 | /* Set frame format: asynchronous, 8data, no parity, 1stop bit */ |
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| 326 | #ifdef URSEL |
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| 327 | UCSRC = (1<<URSEL)|(3<<UCSZ0); |
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| 328 | #else |
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| 329 | UCSRC = (3<<UCSZ0); |
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| 330 | #endif |
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| 331 | |||
| 332 | #elif defined (ATMEGA_USART0 ) |
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| 333 | /* Set baud rate */ |
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| 334 | if ( baudrate & 0x8000 ) |
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| 335 | { |
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| 336 | UART0_STATUS = (1<<U2X0); //Enable 2x speed |
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| 337 | baudrate &= ~0x8000; |
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| 338 | } |
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| 339 | UBRR0H = (unsigned char)(baudrate>>8); |
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| 340 | UBRR0L = (unsigned char) baudrate; |
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| 341 | |||
| 342 | /* Enable USART receiver and transmitter and receive complete interrupt */ |
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| 343 | UART0_CONTROL = _BV(RXCIE0)|(1<<RXEN0)|(1<<TXEN0); |
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| 344 | |||
| 1578 | arune | 345 | /* Set frame format */ |
| 346 | uart_updateConfig(); |
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| 361 | andfri | 347 | |
| 348 | #elif defined ( ATMEGA_UART ) |
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| 349 | /* set baud rate */ |
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| 350 | if ( baudrate & 0x8000 ) |
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| 351 | { |
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| 352 | UART0_STATUS = (1<<U2X); //Enable 2x speed |
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| 353 | baudrate &= ~0x8000; |
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| 354 | } |
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| 355 | UBRRHI = (unsigned char)(baudrate>>8); |
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| 356 | UBRR = (unsigned char) baudrate; |
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| 357 | |||
| 358 | /* Enable UART receiver and transmitter and receive complete interrupt */ |
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| 359 | UART0_CONTROL = _BV(RXCIE)|(1<<RXEN)|(1<<TXEN); |
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| 360 | |||
| 361 | #endif |
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| 362 | |||
| 363 | }/* uart_init */ |
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| 364 | |||
| 365 | |||
| 366 | /************************************************************************* |
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| 367 | Function: uart_getc() |
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| 368 | Purpose: return byte from ringbuffer |
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| 369 | Returns: lower byte: received byte from ringbuffer |
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| 370 | higher byte: last receive error |
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| 371 | **************************************************************************/ |
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| 372 | unsigned int uart_getc(void) |
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| 373 | { |
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| 374 | unsigned char tmptail; |
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| 375 | unsigned char data; |
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| 376 | |||
| 377 | |||
| 378 | if ( UART_RxHead == UART_RxTail ) { |
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| 379 | return UART_NO_DATA; /* no data available */ |
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| 380 | } |
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| 381 | |||
| 382 | /* calculate /store buffer index */ |
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| 383 | tmptail = (UART_RxTail + 1) & UART_RX_BUFFER_MASK; |
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| 384 | UART_RxTail = tmptail; |
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| 385 | |||
| 386 | /* get data from receive buffer */ |
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| 387 | data = UART_RxBuf[tmptail]; |
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| 388 | |||
| 389 | return (UART_LastRxError << 8) + data; |
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| 390 | |||
| 391 | }/* uart_getc */ |
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| 392 | |||
| 393 | |||
| 394 | /************************************************************************* |
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| 395 | Function: uart_putc() |
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| 396 | Purpose: write byte to ringbuffer for transmitting via UART |
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| 397 | Input: byte to be transmitted |
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| 398 | Returns: none |
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| 399 | **************************************************************************/ |
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| 400 | void uart_putc(unsigned char data) |
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| 401 | { |
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| 402 | unsigned char tmphead; |
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| 403 | |||
| 404 | |||
| 405 | tmphead = (UART_TxHead + 1) & UART_TX_BUFFER_MASK; |
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| 406 | |||
| 407 | while ( tmphead == UART_TxTail ){ |
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| 408 | ;/* wait for free space in buffer */ |
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| 409 | } |
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| 410 | |||
| 411 | UART_TxBuf[tmphead] = data; |
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| 412 | UART_TxHead = tmphead; |
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| 413 | |||
| 414 | /* enable UDRE interrupt */ |
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| 415 | UART0_CONTROL |= _BV(UART0_UDRIE); |
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| 416 | |||
| 417 | }/* uart_putc */ |
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| 418 | |||
| 419 | |||
| 420 | /************************************************************************* |
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| 421 | Function: uart_puts() |
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| 422 | Purpose: transmit string to UART |
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| 423 | Input: string to be transmitted |
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| 424 | Returns: none |
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| 425 | **************************************************************************/ |
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| 426 | void uart_puts(const char *s ) |
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| 427 | { |
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| 428 | while (*s) |
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| 429 | uart_putc(*s++); |
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| 430 | |||
| 431 | }/* uart_puts */ |
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| 432 | |||
| 433 | |||
| 434 | /************************************************************************* |
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| 435 | Function: uart_puts_p() |
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| 436 | Purpose: transmit string from program memory to UART |
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| 437 | Input: program memory string to be transmitted |
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| 438 | Returns: none |
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| 439 | **************************************************************************/ |
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| 440 | void uart_puts_p(const char *progmem_s ) |
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| 441 | { |
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| 442 | register char c; |
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| 443 | |||
| 444 | while ( (c = pgm_read_byte(progmem_s++)) ) |
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| 445 | uart_putc(c); |
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| 446 | |||
| 447 | }/* uart_puts_p */ |
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| 448 | |||
| 449 | |||
| 450 | /* |
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| 451 | * these functions are only for ATmegas with two USART |
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| 452 | */ |
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| 453 | #if defined( ATMEGA_USART1 ) |
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| 454 | |||
| 1695 | arune | 455 | ISR(UART1_RECEIVE_INTERRUPT) |
| 361 | andfri | 456 | /************************************************************************* |
| 457 | Function: UART1 Receive Complete interrupt |
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| 458 | Purpose: called when the UART1 has received a character |
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| 459 | **************************************************************************/ |
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| 460 | { |
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| 461 | unsigned char tmphead; |
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| 462 | unsigned char data; |
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| 463 | unsigned char usr; |
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| 464 | unsigned char lastRxError; |
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| 465 | |||
| 466 | |||
| 467 | /* read UART status register and UART data register */ |
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| 468 | usr = UART1_STATUS; |
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| 469 | data = UART1_DATA; |
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| 470 | |||
| 471 | /* */ |
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| 472 | lastRxError = (usr & (_BV(FE1)|_BV(DOR1)) ); |
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| 473 | |||
| 474 | /* calculate buffer index */ |
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| 475 | tmphead = ( UART1_RxHead + 1) & UART_RX_BUFFER_MASK; |
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| 476 | |||
| 477 | if ( tmphead == UART1_RxTail ) { |
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| 478 | /* error: receive buffer overflow */ |
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| 479 | lastRxError = UART_BUFFER_OVERFLOW >> 8; |
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| 480 | }else{ |
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| 481 | /* store new index */ |
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| 482 | UART1_RxHead = tmphead; |
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| 483 | /* store received data in buffer */ |
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| 484 | UART1_RxBuf[tmphead] = data; |
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| 485 | } |
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| 486 | UART1_LastRxError = lastRxError; |
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| 487 | } |
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| 488 | |||
| 489 | |||
| 1695 | arune | 490 | ISR(UART1_TRANSMIT_INTERRUPT) |
| 361 | andfri | 491 | /************************************************************************* |
| 492 | Function: UART1 Data Register Empty interrupt |
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| 493 | Purpose: called when the UART1 is ready to transmit the next byte |
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| 494 | **************************************************************************/ |
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| 495 | { |
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| 496 | unsigned char tmptail; |
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| 497 | |||
| 498 | |||
| 499 | if ( UART1_TxHead != UART1_TxTail) { |
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| 500 | /* calculate and store new buffer index */ |
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| 501 | tmptail = (UART1_TxTail + 1) & UART_TX_BUFFER_MASK; |
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| 502 | UART1_TxTail = tmptail; |
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| 503 | /* get one byte from buffer and write it to UART */ |
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| 504 | UART1_DATA = UART1_TxBuf[tmptail]; /* start transmission */ |
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| 505 | }else{ |
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| 506 | /* tx buffer empty, disable UDRE interrupt */ |
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| 507 | UART1_CONTROL &= ~_BV(UART1_UDRIE); |
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| 508 | } |
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| 509 | } |
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| 510 | |||
| 511 | |||
| 512 | /************************************************************************* |
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| 513 | Function: uart1_init() |
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| 514 | Purpose: initialize UART1 and set baudrate |
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| 515 | Input: baudrate using macro UART_BAUD_SELECT() |
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| 516 | Returns: none |
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| 517 | **************************************************************************/ |
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| 518 | void uart1_init(unsigned int baudrate) |
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| 519 | { |
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| 520 | UART1_TxHead = 0; |
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| 521 | UART1_TxTail = 0; |
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| 522 | UART1_RxHead = 0; |
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| 523 | UART1_RxTail = 0; |
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| 524 | |||
| 525 | |||
| 526 | /* Set baud rate */ |
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| 527 | if ( baudrate & 0x8000 ) |
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| 528 | { |
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| 529 | UART1_STATUS = (1<<U2X1); //Enable 2x speed |
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| 530 | baudrate &= ~0x8000; |
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| 531 | } |
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| 532 | UBRR1H = (unsigned char)(baudrate>>8); |
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| 533 | UBRR1L = (unsigned char) baudrate; |
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| 534 | |||
| 535 | /* Enable USART receiver and transmitter and receive complete interrupt */ |
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| 536 | UART1_CONTROL = _BV(RXCIE1)|(1<<RXEN1)|(1<<TXEN1); |
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| 537 | |||
| 1578 | arune | 538 | /* Set frame format: asynchronous, 8data, no parity, 1stop bit */ |
| 539 | #ifdef URSEL1 |
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| 540 | UCSR1C = (1<<URSEL1)|(3<<UCSZ10); |
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| 541 | #else |
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| 542 | UCSR1C = (3<<UCSZ10); |
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| 543 | #endif |
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| 544 | |||
| 361 | andfri | 545 | }/* uart_init */ |
| 546 | |||
| 547 | |||
| 548 | /************************************************************************* |
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| 549 | Function: uart1_getc() |
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| 550 | Purpose: return byte from ringbuffer |
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| 551 | Returns: lower byte: received byte from ringbuffer |
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| 552 | higher byte: last receive error |
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| 553 | **************************************************************************/ |
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| 554 | unsigned int uart1_getc(void) |
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| 555 | { |
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| 556 | unsigned char tmptail; |
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| 557 | unsigned char data; |
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| 558 | |||
| 559 | |||
| 560 | if ( UART1_RxHead == UART1_RxTail ) { |
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| 561 | return UART_NO_DATA; /* no data available */ |
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| 562 | } |
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| 563 | |||
| 564 | /* calculate /store buffer index */ |
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| 565 | tmptail = (UART1_RxTail + 1) & UART_RX_BUFFER_MASK; |
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| 566 | UART1_RxTail = tmptail; |
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| 567 | |||
| 568 | /* get data from receive buffer */ |
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| 569 | data = UART1_RxBuf[tmptail]; |
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| 570 | |||
| 571 | return (UART1_LastRxError << 8) + data; |
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| 572 | |||
| 573 | }/* uart1_getc */ |
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| 574 | |||
| 575 | |||
| 576 | /************************************************************************* |
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| 577 | Function: uart1_putc() |
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| 578 | Purpose: write byte to ringbuffer for transmitting via UART |
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| 579 | Input: byte to be transmitted |
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| 580 | Returns: none |
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| 581 | **************************************************************************/ |
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| 582 | void uart1_putc(unsigned char data) |
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| 583 | { |
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| 584 | unsigned char tmphead; |
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| 585 | |||
| 586 | |||
| 587 | tmphead = (UART1_TxHead + 1) & UART_TX_BUFFER_MASK; |
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| 588 | |||
| 589 | while ( tmphead == UART1_TxTail ){ |
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| 590 | ;/* wait for free space in buffer */ |
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| 591 | } |
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| 592 | |||
| 593 | UART1_TxBuf[tmphead] = data; |
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| 594 | UART1_TxHead = tmphead; |
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| 595 | |||
| 596 | /* enable UDRE interrupt */ |
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| 597 | UART1_CONTROL |= _BV(UART1_UDRIE); |
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| 598 | |||
| 599 | }/* uart1_putc */ |
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| 600 | |||
| 601 | |||
| 602 | /************************************************************************* |
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| 603 | Function: uart1_puts() |
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| 604 | Purpose: transmit string to UART1 |
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| 605 | Input: string to be transmitted |
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| 606 | Returns: none |
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| 607 | **************************************************************************/ |
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| 608 | void uart1_puts(const char *s ) |
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| 609 | { |
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| 610 | while (*s) |
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| 611 | uart1_putc(*s++); |
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| 612 | |||
| 613 | }/* uart1_puts */ |
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| 614 | |||
| 615 | |||
| 616 | /************************************************************************* |
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| 617 | Function: uart1_puts_p() |
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| 618 | Purpose: transmit string from program memory to UART1 |
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| 619 | Input: program memory string to be transmitted |
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| 620 | Returns: none |
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| 621 | **************************************************************************/ |
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| 622 | void uart1_puts_p(const char *progmem_s ) |
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| 623 | { |
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| 624 | register char c; |
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| 625 | |||
| 626 | while ( (c = pgm_read_byte(progmem_s++)) ) |
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| 627 | uart1_putc(c); |
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| 628 | |||
| 629 | }/* uart1_puts_p */ |
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| 630 | |||
| 631 | |||
| 632 | #endif |