Rev 2095 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | SVN | RSS feed
| Rev 2095 | Rev 2108 | ||
|---|---|---|---|
| Line 21... | Line 21... | ||
| 21 | # will give 120Hz PWM, adjust CS to change frequency |
21 | # will give 120Hz PWM, adjust CS to change frequency |
| 22 | 22 | ||
| 23 | # for channel 3 or 4: |
23 | # for channel 3 or 4: |
| 24 | # COM=2, WGM= 1, CS=3 |
24 | # COM=2, WGM= 1, CS=3 |
| 25 | # will give 240Hz PWM, adjust CS to change frequency |
25 | # will give 240Hz PWM, adjust CS to change frequency |
| - | 26 | ||
| - | 27 | #Channel 1 and 2 is attached to the 16 bit timer 1 |
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| - | 28 | #Channel 3 and 4 is attached to the 8 bit timer 0 |
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| - | 29 | ||
| - | 30 | #### PWM Channel 1 and 2 #### |
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| - | 31 | # COM-modes: |
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| - | 32 | # In Fast PWM mode: |
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| - | 33 | # 0 - Disabled |
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| - | 34 | # 1 - Toggle OC1A on compare match, OC1B disabled (if WGM = 14 or 15) |
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| - | 35 | # 2 - Clear output on Compare match, set at bottom (non-inverting) |
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| - | 36 | # 3 - Set output on Compare match, clear at bottom (inverting) |
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| - | 37 | # In Phase correct mode: |
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| - | 38 | # 0 - Disabled |
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| - | 39 | # 1 - Toggle OC1A on compare match, OC1B disabled (if WGM = 9 or 11) |
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| - | 40 | # 2 - Clear output on compare match when upcounting |
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| - | 41 | # set when downcounting |
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| - | 42 | # 3 - Set output on compare match when upcounting |
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| - | 43 | # clear when downcounting |
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| - | 44 | # |
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| - | 45 | # WGM-modes: |
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| - | 46 | # Mode "TOP" "Update Output" "Name" |
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| - | 47 | # 0 - 0xFFFF Immediate Normal |
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| - | 48 | # 1 - 0x00FF Top PWM, Phase correct, 8-bit |
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| - | 49 | # 2 - 0x01FF Top PWM, Phase correct, 9-bit |
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| - | 50 | # 3 - 0x03FF Top PWM, Phase correct, 10-bit |
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| - | 51 | # 4 - 0CR1A Immediate CTC |
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| - | 52 | # 5 - 0x00FF Bottom PWM, Fast, 8-bit |
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| - | 53 | # 6 - 0x01FF Bottom PWM, Fast, 9-bit |
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| - | 54 | # 7 - 0x03FF Bottom PWM, Fast, 10-bit |
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| - | 55 | # 8 - ICR1 Bottom PWM, Phase and frequency correct |
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| - | 56 | # 9 - OCR1A Bottom PWM, Phase and frequency correct |
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| - | 57 | # 10 - ICR1 Top PWM, Phase correct |
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| - | 58 | # 11 - OCR1A Top PWM, Phase correct |
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| - | 59 | # 12 - ICR1 Immediate CTC |
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| - | 60 | # 13 - Reserved |
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| - | 61 | # 14 - ICR1 Bottom PWM, Fast |
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| - | 62 | # 15 - OCR1A Bottom PWM, Fast |
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| 26 | 63 | ||
| 27 | #### PWM Channel 1, EXP_B, Timer1, OC1B #### |
64 | #### PWM Channel 1, EXP_B, Timer1, OC1B #### |
| 28 | 65 | ||
| 29 | # Select Compare Output Mode, act_hwPWM_CHx_COM |
66 | # Select Compare Output Mode, act_hwPWM_CHx_COM |
| 30 | # Set to 0 to disable this channel |
67 | # Set to 0 to disable this channel |
| 31 | # See datasheet for more information |
68 | # See datasheet for more information |
| 32 | act_hwPWM_CH1_COM=0 |
69 | act_hwPWM_CH1_COM=0 |
| 33 | 70 | ||
| 34 | # Select Waveform Generation Mode, act_hwPWM_CHx_WGM |
71 | # Select Waveform Generation Mode, act_hwPWM_CHx_WGM |
| 35 | # See table datasheet for information |
72 | # See table datasheet for information |
| 36 | act_hwPWM_CH1_WGM=1 |
73 | act_hwPWM_CH1_WGM=1 |
| 37 | 74 | ||
| 38 | # Select Clock Prescaler, act_hwPWM_CHx_CS |
75 | # Select Clock Prescaler, act_hwPWM_CHx_CS |
| 39 | # 1 divide by 1 2 divide by 8 |
76 | # 1 divide by 1 2 divide by 8 |
| 40 | # 3 divide by 32 4 divide by 64 |
77 | # 3 divide by 32 4 divide by 64 |
| 41 | # 5 divide by 128 6 divide by 256 |
78 | # 5 divide by 128 6 divide by 256 |
| 42 | # 7 divide by 1024 |
79 | # 7 divide by 1024 |
| Line 49... | Line 86... | ||
| 49 | #### PWM Channel 2, EXP_C, Timer1, OC1A #### |
86 | #### PWM Channel 2, EXP_C, Timer1, OC1A #### |
| 50 | act_hwPWM_CH2_COM=0 |
87 | act_hwPWM_CH2_COM=0 |
| 51 | act_hwPWM_CH2_WGM=1 |
88 | act_hwPWM_CH2_WGM=1 |
| 52 | act_hwPWM_CH2_CS=1 |
89 | act_hwPWM_CH2_CS=1 |
| 53 | act_hwPWM_CH3_LED=0 |
90 | act_hwPWM_CH3_LED=0 |
| - | 91 | ||
| - | 92 | #### PWM Channel 3 and 4 #### |
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| - | 93 | # COM-modes: |
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| - | 94 | # In Fast PWM mode: |
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| - | 95 | # 0 - Disabled |
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| - | 96 | # 1 - Toggle output on compare match (if WGM >= 4) |
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| - | 97 | # 2 - Clear output on Compare match, set at bottom (non-inverting) |
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| - | 98 | # 3 - Set output on Compare match, clear at bottom (inverting) |
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| - | 99 | # In Phase correct mode: |
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| - | 100 | # 0 - Disabled |
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| - | 101 | # 1 - Toggle output on compare match (if WGM >= 4) |
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| - | 102 | # 2 - Clear output on compare match when upcounting |
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| - | 103 | # set when downcounting |
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| - | 104 | # 3 - Set output on compare match when upcounting |
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| - | 105 | # clear when downcounting |
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| - | 106 | # |
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| - | 107 | # WGM-modes: |
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| - | 108 | # Mode "TOP" "Update Output" "Name" |
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| - | 109 | # 0 - 0xFF Immediate Normal |
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| - | 110 | # 1 - 0xFF Top PWM, Phase correct |
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| - | 111 | # 2 - 0CRA Immediate CTC |
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| - | 112 | # 3 - 0xFF Bottom PWM, Fast |
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| - | 113 | # 4 - Reserved |
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| - | 114 | # 5 - OCRA Top PWM, Phase correct |
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| - | 115 | # 6 - Reserved |
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| - | 116 | # 7 - OCRA Bottom PWM, Fast |
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| 54 | 117 | ||
| 55 | #### PWM Channel 3, EXP_F, Timer0, OC0A #### |
118 | #### PWM Channel 3, EXP_F, Timer0, OC0A #### |
| 56 | act_hwPWM_CH3_COM=0 |
119 | act_hwPWM_CH3_COM=0 |
| 57 | act_hwPWM_CH3_WGM=1 |
120 | act_hwPWM_CH3_WGM=1 |
| 58 | act_hwPWM_CH3_CS=1 |
121 | act_hwPWM_CH3_CS=1 |