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| Rev 1755 | Rev 1757 | ||
|---|---|---|---|
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| 1 | 1 | ||
| 2 | #include "sns_irTransceive.h" |
2 | #include "sns_irTransceive.h" |
| - | 3 | ||
| - | 4 | #ifdef sns_irTransceive_USEEEPROM |
|
| - | 5 | #include "sns_irTransceive_eeprom.h" |
|
| - | 6 | struct eeprom_sns_irTransceive EEMEM eeprom_sns_irTransceive = |
|
| - | 7 | { |
|
| - | 8 | { |
|
| - | 9 | /* Define initialization values on the EEPROM variables here. |
|
| - | 10 | This will generate a *.eep file that can be used to store this values to the node, can in future be done with a EEPROM module and the make-scrips. |
|
| - | 11 | Write the values in the exact same order as the struct is defined in the *.h file. */ |
|
| - | 12 | CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, |
|
| - | 13 | 0, |
|
| - | 14 | CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, |
|
| - | 15 | 0, |
|
| - | 16 | CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, |
|
| - | 17 | 0, |
|
| - | 18 | }, |
|
| - | 19 | 0 /* crc, must be a correct value, but this will also be handled by the EEPROM module or make scripts */ |
|
| - | 20 | }; |
|
| - | 21 | #endif |
|
| 3 | 22 | ||
| 4 | #if IR_RX_ENABLE==1 |
23 | #if IR_RX_ENABLE==1 |
| 5 | struct { |
24 | struct { |
| 6 | uint8_t state; |
25 | uint8_t state; |
| 7 | uint16_t *rxbuf; |
26 | uint16_t *rxbuf; |
| Line 22... | Line 41... | ||
| 22 | Ir_Protocol_Data_t proto; |
41 | Ir_Protocol_Data_t proto; |
| 23 | uint8_t stopSend; |
42 | uint8_t stopSend; |
| 24 | uint8_t sendComplete; |
43 | uint8_t sendComplete; |
| 25 | } irTxChannel[IR_SUPPORTED_NUM_CHANNELS]; |
44 | } irTxChannel[IR_SUPPORTED_NUM_CHANNELS]; |
| 26 | #endif |
45 | #endif |
| 27 | 46 | ||
| 28 | uint16_t buf[3][MAX_NR_TIMES]; |
47 | uint16_t buf[3][MAX_NR_TIMES]; |
| 29 | 48 | ||
| 30 | StdCan_Msg_t irTxMsg; |
49 | StdCan_Msg_t irTxMsg; |
| 31 | 50 | ||
| 32 | #if (sns_irTransceive_SEND_DEBUG==1) |
51 | #if (sns_irTransceive_SEND_DEBUG==1) |
| Line 61... | Line 80... | ||
| 61 | if (lastpacketcnt > 0) { |
80 | if (lastpacketcnt > 0) { |
| 62 | dbgIrTxMsg.Length = lastpacketcnt<<1; |
81 | dbgIrTxMsg.Length = lastpacketcnt<<1; |
| 63 | for (uint8_t i = 0; i < lastpacketcnt; i++) { |
82 | for (uint8_t i = 0; i < lastpacketcnt; i++) { |
| 64 | dbgIrTxMsg.Data[i<<1] = (buffer[(len&0xfc)|i]>>8)&0xff; |
83 | dbgIrTxMsg.Data[i<<1] = (buffer[(len&0xfc)|i]>>8)&0xff; |
| 65 | dbgIrTxMsg.Data[(i<<1)+1] = (buffer[(len&0xfc)|i]>>0)&0xff; |
84 | dbgIrTxMsg.Data[(i<<1)+1] = (buffer[(len&0xfc)|i]>>0)&0xff; |
| 66 | } |
85 | } |
| 67 | /* buffers will be filled when sending more than 2-3 messages, so retry until sent */ |
86 | /* buffers will be filled when sending more than 2-3 messages, so retry until sent */ |
| 68 | while (StdCan_Put(&dbgIrTxMsg) != StdCan_Ret_OK) {} |
87 | while (StdCan_Put(&dbgIrTxMsg) != StdCan_Ret_OK) {} |
| 69 | _delay_ms(1); |
88 | _delay_ms(1); |
| 70 | } |
89 | } |
| 71 | 90 | ||
| 72 | } |
91 | } |
| 73 | #endif |
92 | #endif |
| - | 93 | ||
| 74 | 94 | ||
| 75 | #if IR_RX_ENABLE==1 |
95 | #if IR_RX_ENABLE==1 |
| 76 | void sns_irTransceive_RX_done_callback(uint8_t channel, uint16_t *buffer, uint8_t len) |
96 | void sns_irTransceive_RX_done_callback(uint8_t channel, uint16_t *buffer, uint8_t len) |
| 77 | { |
97 | { |
| 78 | if (channel < IR_SUPPORTED_NUM_CHANNELS) |
98 | if (channel < IR_SUPPORTED_NUM_CHANNELS) |
| 79 | { |
99 | { |
| 80 | irRxChannel[channel].newData = TRUE; |
100 | irRxChannel[channel].newData = TRUE; |
| 81 | irRxChannel[channel].rxlen = len; |
101 | irRxChannel[channel].rxlen = len; |
| 82 | } |
102 | } |
| 83 | } |
103 | } |
| 84 | #endif |
104 | #endif |
| - | 105 | ||
| 85 | 106 | ||
| 86 | #if IR_TX_ENABLE==1 |
107 | #if IR_TX_ENABLE==1 |
| 87 | void sns_irTransceive_TX_done_callback(uint8_t channel) |
108 | void sns_irTransceive_TX_done_callback(uint8_t channel) |
| 88 | { |
109 | { |
| 89 | if (channel < IR_SUPPORTED_NUM_CHANNELS) |
110 | if (channel < IR_SUPPORTED_NUM_CHANNELS) |
| 90 | { |
111 | { |
| 91 | irTxChannel[channel].sendComplete = TRUE; |
112 | irTxChannel[channel].sendComplete = TRUE; |
| 92 | } |
113 | } |
| 93 | } |
114 | } |
| - | 115 | #endif |
|
| - | 116 | ||
| - | 117 | ||
| - | 118 | void sns_irTransceive_setConfig(uint8_t channel, uint8_t config, uint8_t power) |
|
| - | 119 | { |
|
| - | 120 | if (channel < IR_SUPPORTED_NUM_CHANNELS && config <= CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE && power < 4) |
|
| - | 121 | { |
|
| - | 122 | #if IR_RX_ENABLE==1 |
|
| - | 123 | if (config == CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE) |
|
| - | 124 | { |
|
| - | 125 | #if IR_TX_ENABLE==1 |
|
| - | 126 | irTxChannel[channel].state = sns_irTransceive_STATE_DISABLED; |
|
| - | 127 | #endif |
|
| - | 128 | irRxChannel[channel].rxbuf = buf[channel]; |
|
| - | 129 | switch (channel) |
|
| - | 130 | { |
|
| - | 131 | case 0: |
|
| - | 132 | gpio_clr_pin(sns_irTransceive_VCC_EN0_PIN); |
|
| - | 133 | IrTransceiver_InitRxChannel(channel, irRxChannel[channel].rxbuf, sns_irTransceive_RX_done_callback, sns_irTransceive_RX0_PCINT, sns_irTransceive_RX0_PIN); |
|
| - | 134 | break; |
|
| - | 135 | case 1: |
|
| - | 136 | gpio_clr_pin(sns_irTransceive_VCC_EN1_PIN); |
|
| - | 137 | IrTransceiver_InitRxChannel(channel, irRxChannel[channel].rxbuf, sns_irTransceive_RX_done_callback, sns_irTransceive_RX1_PCINT, sns_irTransceive_RX1_PIN); |
|
| - | 138 | break; |
|
| - | 139 | case 2: |
|
| - | 140 | gpio_clr_pin(sns_irTransceive_VCC_EN2_PIN); |
|
| - | 141 | IrTransceiver_InitRxChannel(channel, irRxChannel[channel].rxbuf, sns_irTransceive_RX_done_callback, sns_irTransceive_RX2_PCINT, sns_irTransceive_RX2_PIN); |
|
| - | 142 | break; |
|
| - | 143 | } |
|
| - | 144 | irRxChannel[channel].state = sns_irTransceive_STATE_RECEIVING; |
|
| - | 145 | } |
|
| - | 146 | #endif |
|
| - | 147 | ||
| - | 148 | #if IR_TX_ENABLE==1 |
|
| - | 149 | if (config == CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_TRANSMIT) |
|
| - | 150 | { |
|
| - | 151 | #if IR_RX_ENABLE==1 |
|
| - | 152 | irRxChannel[channel].state = sns_irTransceive_STATE_DISABLED; |
|
| - | 153 | #endif |
|
| - | 154 | ||
| - | 155 | irTxChannel[channel].txbuf = buf[channel]; |
|
| - | 156 | switch (channel) |
|
| - | 157 | { |
|
| - | 158 | case 0: |
|
| - | 159 | #if IR_RX_ENABLE==1 |
|
| - | 160 | gpio_set_pin(sns_irTransceive_VCC_EN0_PIN); |
|
| - | 161 | IrTransceiver_DeInitRxChannel(channel, sns_irTransceive_RX0_PCINT, sns_irTransceive_RX0_PIN); |
|
| - | 162 | #endif |
|
| - | 163 | IrTransceiver_InitTxChannel(channel, sns_irTransceive_TX_done_callback, sns_irTransceive_TX0_PIN); |
|
| - | 164 | ||
| - | 165 | #if sns_irTransceive_ENABLE_PCA95xx==1 |
|
| - | 166 | Pca95xx_set_out(sns_irTransceive_TX0_PWRl); |
|
| - | 167 | Pca95xx_set_out(sns_irTransceive_TX0_PWRh); |
|
| - | 168 | if (power&0x1) |
|
| - | 169 | { |
|
| - | 170 | Pca95xx_set_in(sns_irTransceive_TX0_PWRl); |
|
| - | 171 | } |
|
| - | 172 | if (power&0x2) |
|
| - | 173 | { |
|
| - | 174 | Pca95xx_set_in(sns_irTransceive_TX0_PWRh); |
|
| - | 175 | } |
|
| - | 176 | #endif |
|
| - | 177 | break; |
|
| - | 178 | case 1: |
|
| - | 179 | #if IR_RX_ENABLE==1 |
|
| - | 180 | gpio_set_pin(sns_irTransceive_VCC_EN1_PIN); |
|
| - | 181 | IrTransceiver_DeInitRxChannel(channel, sns_irTransceive_RX1_PCINT, sns_irTransceive_RX1_PIN); |
|
| - | 182 | #endif |
|
| - | 183 | IrTransceiver_InitTxChannel(channel, sns_irTransceive_TX_done_callback, sns_irTransceive_TX1_PIN); |
|
| - | 184 | ||
| - | 185 | #if sns_irTransceive_ENABLE_PCA95xx==1 |
|
| - | 186 | Pca95xx_set_out(sns_irTransceive_TX1_PWRl); |
|
| - | 187 | Pca95xx_set_out(sns_irTransceive_TX1_PWRh); |
|
| - | 188 | if (power&0x1) |
|
| - | 189 | { |
|
| - | 190 | Pca95xx_set_in(sns_irTransceive_TX1_PWRl); |
|
| - | 191 | } |
|
| - | 192 | if (power&0x2) |
|
| - | 193 | { |
|
| - | 194 | Pca95xx_set_in(sns_irTransceive_TX1_PWRh); |
|
| - | 195 | } |
|
| - | 196 | #endif |
|
| - | 197 | break; |
|
| - | 198 | case 2: |
|
| - | 199 | #if IR_RX_ENABLE==1 |
|
| - | 200 | gpio_set_pin(sns_irTransceive_VCC_EN2_PIN); |
|
| - | 201 | IrTransceiver_DeInitRxChannel(channel, sns_irTransceive_RX2_PCINT, sns_irTransceive_RX2_PIN); |
|
| - | 202 | #endif |
|
| - | 203 | IrTransceiver_InitTxChannel(channel, sns_irTransceive_TX_done_callback, sns_irTransceive_TX2_PIN); |
|
| - | 204 | ||
| - | 205 | #if sns_irTransceive_ENABLE_PCA95xx==1 |
|
| - | 206 | Pca95xx_set_out(sns_irTransceive_TX2_PWRl); |
|
| - | 207 | Pca95xx_set_out(sns_irTransceive_TX2_PWRh); |
|
| - | 208 | if (power&0x1) |
|
| - | 209 | { |
|
| - | 210 | Pca95xx_set_in(sns_irTransceive_TX2_PWRl); |
|
| - | 211 | } |
|
| - | 212 | if (power&0x2) |
|
| - | 213 | { |
|
| - | 214 | Pca95xx_set_in(sns_irTransceive_TX2_PWRh); |
|
| - | 215 | } |
|
| - | 216 | #endif |
|
| - | 217 | break; |
|
| - | 218 | } |
|
| - | 219 | irTxChannel[channel].state = sns_irTransceive_STATE_START_IDLE; |
|
| - | 220 | } |
|
| 94 | #endif |
221 | #endif |
| - | 222 | } |
|
| - | 223 | } |
|
| - | 224 | ||
| 95 | 225 | ||
| 96 | void sns_irTransceive_Init(void) |
226 | void sns_irTransceive_Init(void) |
| 97 | { |
227 | { |
| 98 | /* Debug IO, PB7 */ |
- | |
| 99 | /*gpio_set_out(GPIO_D7); |
- | |
| 100 | gpio_set_pin(GPIO_D7); |
- | |
| 101 | gpio_set_out(GPIO_B0); |
- | |
| 102 | gpio_set_pin(GPIO_B0); |
- | |
| 103 | gpio_set_out(GPIO_B7); |
- | |
| 104 | gpio_set_pin(GPIO_B7); |
- | |
| 105 | */ |
- | |
| 106 | StdCan_Set_class(irTxMsg.Header, CAN_MODULE_CLASS_SNS); |
228 | StdCan_Set_class(irTxMsg.Header, CAN_MODULE_CLASS_SNS); |
| 107 | StdCan_Set_direction(irTxMsg.Header, DIRECTIONFLAG_FROM_OWNER); |
229 | StdCan_Set_direction(irTxMsg.Header, DIRECTIONFLAG_FROM_OWNER); |
| 108 | irTxMsg.Header.ModuleType = CAN_MODULE_TYPE_SNS_IRTRANSCEIVE; |
230 | irTxMsg.Header.ModuleType = CAN_MODULE_TYPE_SNS_IRTRANSCEIVE; |
| 109 | irTxMsg.Header.ModuleId = sns_irTransceive_ID; |
231 | irTxMsg.Header.ModuleId = sns_irTransceive_ID; |
| 110 | irTxMsg.Header.Command = CAN_MODULE_CMD_PHYSICAL_IR; |
232 | irTxMsg.Header.Command = CAN_MODULE_CMD_PHYSICAL_IR; |
| Line 129... | Line 251... | ||
| 129 | irTxChannel[i].txlen = 0; |
251 | irTxChannel[i].txlen = 0; |
| 130 | irTxChannel[i].proto.data=0; |
252 | irTxChannel[i].proto.data=0; |
| 131 | irTxChannel[i].proto.repeats=0; |
253 | irTxChannel[i].proto.repeats=0; |
| 132 | irTxChannel[i].proto.framecnt=0; |
254 | irTxChannel[i].proto.framecnt=0; |
| 133 | irTxChannel[i].proto.protocol=0; |
255 | irTxChannel[i].proto.protocol=0; |
| 134 | #endif |
256 | #endif |
| 135 | } |
257 | } |
| 136 | 258 | ||
| 137 | #if IR_RX_ENABLE==1 |
259 | #if IR_RX_ENABLE==1 |
| 138 | irRxChannel[0].timerNum=sns_irTransceive_RX0_REPEATE_TIMER; |
260 | irRxChannel[0].timerNum=sns_irTransceive_RX0_REPEATE_TIMER; |
| 139 | irRxChannel[1].timerNum=sns_irTransceive_RX1_REPEATE_TIMER; |
261 | irRxChannel[1].timerNum=sns_irTransceive_RX1_REPEATE_TIMER; |
| 140 | irRxChannel[2].timerNum=sns_irTransceive_RX2_REPEATE_TIMER; |
262 | irRxChannel[2].timerNum=sns_irTransceive_RX2_REPEATE_TIMER; |
| 141 | #endif |
263 | #endif |
| 142 | 264 | ||
| Line 152... | Line 274... | ||
| 152 | gpio_set_out(sns_irTransceive_VCC_EN1_PIN); |
274 | gpio_set_out(sns_irTransceive_VCC_EN1_PIN); |
| 153 | gpio_set_out(sns_irTransceive_VCC_EN2_PIN); |
275 | gpio_set_out(sns_irTransceive_VCC_EN2_PIN); |
| 154 | gpio_set_pin(sns_irTransceive_VCC_EN0_PIN); |
276 | gpio_set_pin(sns_irTransceive_VCC_EN0_PIN); |
| 155 | gpio_set_pin(sns_irTransceive_VCC_EN1_PIN); |
277 | gpio_set_pin(sns_irTransceive_VCC_EN1_PIN); |
| 156 | gpio_set_pin(sns_irTransceive_VCC_EN2_PIN); |
278 | gpio_set_pin(sns_irTransceive_VCC_EN2_PIN); |
| 157 | 279 | ||
| 158 | #if IR_TX_ENABLE==1 |
280 | #if IR_TX_ENABLE==1 |
| 159 | gpio_set_out(sns_irTransceive_MOD_PIN); |
281 | gpio_set_out(sns_irTransceive_MOD_PIN); |
| 160 | gpio_set_out(sns_irTransceive_TX0_PIN); |
282 | gpio_set_out(sns_irTransceive_TX0_PIN); |
| 161 | gpio_set_out(sns_irTransceive_TX1_PIN); |
283 | gpio_set_out(sns_irTransceive_TX1_PIN); |
| 162 | gpio_set_out(sns_irTransceive_TX2_PIN); |
284 | gpio_set_out(sns_irTransceive_TX2_PIN); |
| 163 | #if IR_TX_ACTIVE_LOW==1 |
285 | #if IR_TX_ACTIVE_LOW==1 |
| 164 | gpio_set_pin(sns_irTransceive_TX0_PIN); |
286 | gpio_set_pin(sns_irTransceive_TX0_PIN); |
| 165 | gpio_set_pin(sns_irTransceive_TX1_PIN); |
287 | gpio_set_pin(sns_irTransceive_TX1_PIN); |
| 166 | gpio_set_pin(sns_irTransceive_TX2_PIN); |
288 | gpio_set_pin(sns_irTransceive_TX2_PIN); |
| 167 | #endif |
289 | #endif |
| 168 | #endif |
290 | #endif |
| 169 | 291 | ||
| 170 | /* IR tx power pins on PCA95xx */ |
292 | /* IR tx power pins on PCA95xx */ |
| 171 | #if sns_irTransceive_ENABLE_PCA95xx==1 |
293 | #if sns_irTransceive_ENABLE_PCA95xx==1 |
| 172 | Pca95xx_Init(0); |
294 | Pca95xx_Init(0); |
| - | 295 | ||
| 173 | Pca95xx_clr_pin(sns_irTransceive_TX0_PWRl); |
296 | Pca95xx_clr_pin(sns_irTransceive_TX0_PWRl); |
| 174 | Pca95xx_set_out(sns_irTransceive_TX0_PWRl); |
297 | Pca95xx_set_out(sns_irTransceive_TX0_PWRl); |
| 175 | Pca95xx_clr_pin(sns_irTransceive_TX0_PWRh); |
298 | Pca95xx_clr_pin(sns_irTransceive_TX0_PWRh); |
| 176 | Pca95xx_set_out(sns_irTransceive_TX0_PWRh); |
299 | Pca95xx_set_out(sns_irTransceive_TX0_PWRh); |
| 177 | 300 | ||
| 178 | Pca95xx_clr_pin(sns_irTransceive_TX1_PWRl); |
301 | Pca95xx_clr_pin(sns_irTransceive_TX1_PWRl); |
| 179 | Pca95xx_set_out(sns_irTransceive_TX1_PWRl); |
302 | Pca95xx_set_out(sns_irTransceive_TX1_PWRl); |
| 180 | Pca95xx_clr_pin(sns_irTransceive_TX1_PWRh); |
303 | Pca95xx_clr_pin(sns_irTransceive_TX1_PWRh); |
| 181 | Pca95xx_set_out(sns_irTransceive_TX1_PWRh); |
304 | Pca95xx_set_out(sns_irTransceive_TX1_PWRh); |
| 182 | 305 | ||
| 183 | Pca95xx_clr_pin(sns_irTransceive_TX2_PWRl); |
306 | Pca95xx_clr_pin(sns_irTransceive_TX2_PWRl); |
| 184 | Pca95xx_set_out(sns_irTransceive_TX2_PWRl); |
307 | Pca95xx_set_out(sns_irTransceive_TX2_PWRl); |
| 185 | Pca95xx_clr_pin(sns_irTransceive_TX2_PWRh); |
308 | Pca95xx_clr_pin(sns_irTransceive_TX2_PWRh); |
| 186 | Pca95xx_set_out(sns_irTransceive_TX2_PWRh); |
309 | Pca95xx_set_out(sns_irTransceive_TX2_PWRh); |
| 187 | #endif |
310 | #endif |
| 188 | 311 | ||
| - | 312 | #ifdef sns_irTransceive_USEEEPROM |
|
| - | 313 | if (EEDATA_OK) |
|
| - | 314 | { |
|
| - | 315 | /* Use stored data to set initial values for the module */ |
|
| - | 316 | sns_irTransceive_setConfig(0, eeprom_read_byte(EEDATA.ch0_config), eeprom_read_byte(EEDATA.ch0_txpower)); |
|
| - | 317 | sns_irTransceive_setConfig(1, eeprom_read_byte(EEDATA.ch1_config), eeprom_read_byte(EEDATA.ch1_txpower)); |
|
| - | 318 | sns_irTransceive_setConfig(2, eeprom_read_byte(EEDATA.ch2_config), eeprom_read_byte(EEDATA.ch2_txpower)); |
|
| - | 319 | } |
|
| - | 320 | else |
|
| - | 321 | { |
|
| - | 322 | /* The CRC of the EEPROM is not correct, store default values and update CRC */ |
|
| - | 323 | eeprom_write_byte_crc(EEDATA.ch0_config, CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, WITHOUT_CRC); |
|
| - | 324 | eeprom_write_byte_crc(EEDATA.ch0_txpower, 0, WITHOUT_CRC); |
|
| - | 325 | eeprom_write_byte_crc(EEDATA.ch1_config, CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, WITHOUT_CRC); |
|
| - | 326 | eeprom_write_byte_crc(EEDATA.ch1_txpower, 0, WITHOUT_CRC); |
|
| - | 327 | eeprom_write_byte_crc(EEDATA.ch2_config, CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, WITHOUT_CRC); |
|
| - | 328 | eeprom_write_byte_crc(EEDATA.ch2_txpower, 0, WITHOUT_CRC); |
|
| - | 329 | EEDATA_UPDATE_CRC; |
|
| - | 330 | } |
|
| - | 331 | #endif |
|
| 189 | } |
332 | } |
| 190 | 333 | ||
| 191 | void sns_irTransceive_Process(void) |
334 | void sns_irTransceive_Process(void) |
| 192 | { |
335 | { |
| 193 | for (uint8_t channel=0; channel < IR_SUPPORTED_NUM_CHANNELS; channel++) |
336 | for (uint8_t channel=0; channel < IR_SUPPORTED_NUM_CHANNELS; channel++) |
| Line 321... | Line 464... | ||
| 321 | } |
464 | } |
| 322 | 465 | ||
| 323 | Timer_SetTimeout(irTxChannel[channel].timerNum, irTxChannel[channel].proto.timeout, TimerTypeOneShot, 0); |
466 | Timer_SetTimeout(irTxChannel[channel].timerNum, irTxChannel[channel].proto.timeout, TimerTypeOneShot, 0); |
| 324 | 467 | ||
| 325 | if (irTxChannel[channel].proto.framecnt != 255) |
468 | if (irTxChannel[channel].proto.framecnt != 255) |
| 326 | { |
469 | { |
| 327 | irTxChannel[channel].proto.framecnt++; |
470 | irTxChannel[channel].proto.framecnt++; |
| 328 | } |
471 | } |
| 329 | 472 | ||
| 330 | irTxChannel[channel].state = sns_irTransceive_STATE_PAUSING; |
473 | irTxChannel[channel].state = sns_irTransceive_STATE_PAUSING; |
| 331 | break; |
474 | break; |
| Line 357... | Line 500... | ||
| 357 | } |
500 | } |
| 358 | #endif |
501 | #endif |
| 359 | 502 | ||
| 360 | } |
503 | } |
| 361 | } |
504 | } |
| - | 505 | ||
| 362 | 506 | ||
| 363 | /* Handle incoming CAN data */ |
507 | /* Handle incoming CAN data */ |
| 364 | void sns_irTransceive_HandleMessage(StdCan_Msg_t *rxMsg) |
508 | void sns_irTransceive_HandleMessage(StdCan_Msg_t *rxMsg) |
| 365 | { |
509 | { |
| 366 | if ( StdCan_Ret_class(rxMsg->Header) == CAN_MODULE_CLASS_SNS && |
510 | if ( StdCan_Ret_class(rxMsg->Header) == CAN_MODULE_CLASS_SNS && |
| Line 384... | Line 528... | ||
| 384 | irTxChannel[channel].proto.data |= rxMsg->Data[3]; |
528 | irTxChannel[channel].proto.data |= rxMsg->Data[3]; |
| 385 | irTxChannel[channel].proto.data = irTxChannel[channel].proto.data<<8; |
529 | irTxChannel[channel].proto.data = irTxChannel[channel].proto.data<<8; |
| 386 | irTxChannel[channel].proto.data |= rxMsg->Data[4]; |
530 | irTxChannel[channel].proto.data |= rxMsg->Data[4]; |
| 387 | irTxChannel[channel].proto.data = irTxChannel[channel].proto.data<<8; |
531 | irTxChannel[channel].proto.data = irTxChannel[channel].proto.data<<8; |
| 388 | irTxChannel[channel].proto.data |= rxMsg->Data[5]; |
532 | irTxChannel[channel].proto.data |= rxMsg->Data[5]; |
| 389 | 533 | ||
| 390 | irTxChannel[channel].state = sns_irTransceive_STATE_START_TRANSMIT; |
534 | irTxChannel[channel].state = sns_irTransceive_STATE_START_TRANSMIT; |
| 391 | } |
535 | } |
| 392 | } |
536 | } |
| 393 | else if ((0xf&rxMsg->Data[0]) == CAN_MODULE_ENUM_PHYSICAL_IR_STATUS_RELEASED && channel < IR_SUPPORTED_NUM_CHANNELS) |
537 | else if ((0xf&rxMsg->Data[0]) == CAN_MODULE_ENUM_PHYSICAL_IR_STATUS_RELEASED && channel < IR_SUPPORTED_NUM_CHANNELS) |
| 394 | { |
538 | { |
| 395 | if (irTxChannel[channel].state != sns_irTransceive_STATE_IDLE) |
539 | if (irTxChannel[channel].state != sns_irTransceive_STATE_IDLE) |
| 396 | { |
540 | { |
| 397 | irTxChannel[channel].stopSend = TRUE; |
541 | irTxChannel[channel].stopSend = TRUE; |
| 398 | } |
542 | } |
| 399 | } |
543 | } |
| 400 | break; |
544 | break; |
| 401 | 545 | ||
| 402 | case CAN_MODULE_CMD_IRTRANSCEIVE_IRCONFIG: |
546 | case CAN_MODULE_CMD_IRTRANSCEIVE_IRCONFIG: |
| 403 | channel = rxMsg->Data[0]>>4; |
547 | channel = rxMsg->Data[0]>>4; |
| 404 | uint8_t config = rxMsg->Data[0] & 0x0f; |
548 | uint8_t config = rxMsg->Data[0] & 0x0f; |
| 405 | uint8_t power = rxMsg->Data[1]>>6; |
549 | uint8_t power = rxMsg->Data[1]>>6; |
| 406 | 550 | ||
| - | 551 | sns_irTransceive_setConfig(channel, config, power); |
|
| - | 552 | ||
| - | 553 | #ifdef sns_irTransceive_USEEEPROM |
|
| 407 | if (channel < IR_SUPPORTED_NUM_CHANNELS && config <= CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE && power < 4) |
554 | if (channel < IR_SUPPORTED_NUM_CHANNELS && config <= CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE && power < 4) |
| 408 | { |
555 | { |
| 409 | #if IR_RX_ENABLE==1 |
- | |
| 410 | if (config == CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE) |
- | |
| 411 | { |
- | |
| 412 | #if IR_TX_ENABLE==1 |
- | |
| 413 | irTxChannel[channel].state = sns_irTransceive_STATE_DISABLED; |
- | |
| 414 | #endif |
- | |
| 415 | irRxChannel[channel].rxbuf = buf[channel]; |
- | |
| 416 | switch (channel) |
- | |
| 417 | { |
- | |
| 418 | case 0: |
- | |
| 419 | gpio_clr_pin(sns_irTransceive_VCC_EN0_PIN); |
- | |
| 420 | IrTransceiver_InitRxChannel(channel, irRxChannel[channel].rxbuf, sns_irTransceive_RX_done_callback, sns_irTransceive_RX0_PCINT, sns_irTransceive_RX0_PIN); |
- | |
| 421 | break; |
- | |
| 422 | case 1: |
- | |
| 423 | gpio_clr_pin(sns_irTransceive_VCC_EN1_PIN); |
- | |
| 424 | IrTransceiver_InitRxChannel(channel, irRxChannel[channel].rxbuf, sns_irTransceive_RX_done_callback, sns_irTransceive_RX1_PCINT, sns_irTransceive_RX1_PIN); |
- | |
| 425 | break; |
- | |
| 426 | case 2: |
- | |
| 427 | gpio_clr_pin(sns_irTransceive_VCC_EN2_PIN); |
- | |
| 428 | IrTransceiver_InitRxChannel(channel, irRxChannel[channel].rxbuf, sns_irTransceive_RX_done_callback, sns_irTransceive_RX2_PCINT, sns_irTransceive_RX2_PIN); |
- | |
| 429 | break; |
- | |
| 430 | } |
- | |
| 431 | irRxChannel[channel].state = sns_irTransceive_STATE_RECEIVING; |
- | |
| 432 | } |
- | |
| 433 | #endif |
- | |
| 434 | - | ||
| 435 | - | ||
| 436 | - | ||
| 437 | // Pca95xx_set_out(sns_irTransceive_TX1_PWRl); |
- | |
| 438 | // Pca95xx_set_out(sns_irTransceive_TX1_PWRh); |
- | |
| 439 | - | ||
| 440 | // Pca95xx_set_out(sns_irTransceive_TX2_PWRl); |
- | |
| 441 | // Pca95xx_set_out(sns_irTransceive_TX2_PWRh); |
- | |
| 442 | - | ||
| 443 | - | ||
| 444 | - | ||
| 445 | #if IR_TX_ENABLE==1 |
- | |
| 446 | if (config == CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_TRANSMIT) |
- | |
| 447 | { |
- | |
| 448 | #if IR_RX_ENABLE==1 |
- | |
| 449 | irRxChannel[channel].state = sns_irTransceive_STATE_DISABLED; |
- | |
| 450 | #endif |
- | |
| 451 | - | ||
| 452 | irTxChannel[channel].txbuf = buf[channel]; |
- | |
| 453 | switch (channel) |
556 | switch (channel) |
| 454 | { |
557 | { |
| 455 | case 0: |
558 | case 0: |
| 456 | #if IR_RX_ENABLE==1 |
- | |
| 457 |
|
559 | eeprom_write_byte_crc(EEDATA.ch0_config, config, WITHOUT_CRC); |
| 458 | IrTransceiver_DeInitRxChannel(channel, sns_irTransceive_RX0_PCINT, sns_irTransceive_RX0_PIN); |
- | |
| 459 | #endif |
- | |
| 460 | IrTransceiver_InitTxChannel(channel, sns_irTransceive_TX_done_callback, sns_irTransceive_TX0_PIN); |
- | |
| 461 | - | ||
| 462 | #if sns_irTransceive_ENABLE_PCA95xx==1 |
- | |
| 463 | Pca95xx_set_out(sns_irTransceive_TX0_PWRl); |
- | |
| 464 |
|
560 | eeprom_write_byte_crc(EEDATA.ch0_txpower, power, WITHOUT_CRC); |
| 465 |
|
561 | break; |
| 466 |
|
562 | case 1: |
| 467 |
|
563 | eeprom_write_byte_crc(EEDATA.ch1_config, config, WITHOUT_CRC); |
| 468 | } |
- | |
| 469 | if (power&0x2) |
- | |
| 470 | { |
- | |
| 471 |
|
564 | eeprom_write_byte_crc(EEDATA.ch1_txpower, power, WITHOUT_CRC); |
| 472 | } |
- | |
| 473 | #endif |
- | |
| 474 | break; |
565 | break; |
| 475 |
|
566 | case 2: |
| 476 | #if IR_RX_ENABLE==1 |
- | |
| 477 |
|
567 | eeprom_write_byte_crc(EEDATA.ch2_config, config, WITHOUT_CRC); |
| 478 | IrTransceiver_DeInitRxChannel(channel, sns_irTransceive_RX1_PCINT, sns_irTransceive_RX1_PIN); |
- | |
| 479 | #endif |
- | |
| 480 | IrTransceiver_InitTxChannel(channel, sns_irTransceive_TX_done_callback, sns_irTransceive_TX1_PIN); |
- | |
| 481 | - | ||
| 482 | #if sns_irTransceive_ENABLE_PCA95xx==1 |
- | |
| 483 | Pca95xx_set_out(sns_irTransceive_TX1_PWRl); |
- | |
| 484 | Pca95xx_set_out(sns_irTransceive_TX1_PWRh); |
- | |
| 485 | if (power&0x1) |
- | |
| 486 | { |
- | |
| 487 |
|
568 | eeprom_write_byte_crc(EEDATA.ch2_txpower, power, WITHOUT_CRC); |
| 488 | } |
- | |
| 489 | if (power&0x2) |
- | |
| 490 |
|
569 | break; |
| 491 | Pca95xx_set_in(sns_irTransceive_TX1_PWRh); |
- | |
| 492 |
|
570 | default: |
| 493 | #endif |
- | |
| 494 | break; |
571 | break; |
| 495 | case 2: |
- | |
| 496 | #if IR_RX_ENABLE==1 |
- | |
| 497 | gpio_set_pin(sns_irTransceive_VCC_EN2_PIN); |
- | |
| 498 | IrTransceiver_DeInitRxChannel(channel, sns_irTransceive_RX2_PCINT, sns_irTransceive_RX2_PIN); |
- | |
| 499 | #endif |
- | |
| 500 | IrTransceiver_InitTxChannel(channel, sns_irTransceive_TX_done_callback, sns_irTransceive_TX2_PIN); |
- | |
| 501 | - | ||
| 502 | #if sns_irTransceive_ENABLE_PCA95xx==1 |
- | |
| 503 | Pca95xx_set_out(sns_irTransceive_TX2_PWRl); |
- | |
| 504 | Pca95xx_set_out(sns_irTransceive_TX2_PWRh); |
- | |
| 505 | if (power&0x1) |
- | |
| 506 | { |
- | |
| 507 | Pca95xx_set_in(sns_irTransceive_TX2_PWRl); |
- | |
| 508 | } |
572 | } |
| 509 |
|
573 | EEDATA_UPDATE_CRC; |
| 510 | { |
- | |
| 511 | Pca95xx_set_in(sns_irTransceive_TX2_PWRh); |
- | |
| 512 | } |
- | |
| 513 | #endif |
- | |
| 514 | break; |
- | |
| 515 | } |
- | |
| 516 | irTxChannel[channel].state = sns_irTransceive_STATE_START_IDLE; |
- | |
| 517 | } |
574 | } |
| 518 | #endif |
575 | #endif |
| 519 | } |
- | |
| 520 | break; |
576 | break; |
| 521 | } |
577 | } |
| 522 | } |
578 | } |
| 523 | } |
579 | } |
| 524 | 580 | ||