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| Rev 1757 | Rev 1771 | ||
|---|---|---|---|
| Line 42... | Line 42... | ||
| 42 | uint8_t stopSend; |
42 | uint8_t stopSend; |
| 43 | uint8_t sendComplete; |
43 | uint8_t sendComplete; |
| 44 | } irTxChannel[IR_SUPPORTED_NUM_CHANNELS]; |
44 | } irTxChannel[IR_SUPPORTED_NUM_CHANNELS]; |
| 45 | #endif |
45 | #endif |
| 46 | 46 | ||
| 47 | uint16_t buf[ |
47 | uint16_t buf[IR_SUPPORTED_NUM_CHANNELS][MAX_NR_TIMES]; |
| 48 | 48 | ||
| 49 | StdCan_Msg_t irTxMsg; |
49 | StdCan_Msg_t irTxMsg; |
| 50 | 50 | ||
| 51 | #if (sns_irTransceive_SEND_DEBUG==1) |
51 | #if (sns_irTransceive_SEND_DEBUG==1) |
| 52 | void send_debug(uint16_t *buffer, uint8_t len) { |
52 | void send_debug(uint16_t *buffer, uint8_t len) { |
| Line 255... | Line 255... | ||
| 255 | irTxChannel[i].proto.protocol=0; |
255 | irTxChannel[i].proto.protocol=0; |
| 256 | #endif |
256 | #endif |
| 257 | } |
257 | } |
| 258 | 258 | ||
| 259 | #if IR_RX_ENABLE==1 |
259 | #if IR_RX_ENABLE==1 |
| - | 260 | // TODO: hardcoded to 3 channels?? /jm |
|
| 260 | irRxChannel[0].timerNum=sns_irTransceive_RX0_REPEATE_TIMER; |
261 | irRxChannel[0].timerNum=sns_irTransceive_RX0_REPEATE_TIMER; |
| 261 | irRxChannel[1].timerNum=sns_irTransceive_RX1_REPEATE_TIMER; |
262 | irRxChannel[1].timerNum=sns_irTransceive_RX1_REPEATE_TIMER; |
| 262 | irRxChannel[2].timerNum=sns_irTransceive_RX2_REPEATE_TIMER; |
263 | irRxChannel[2].timerNum=sns_irTransceive_RX2_REPEATE_TIMER; |
| 263 | #endif |
264 | #endif |
| 264 | 265 | ||
| 265 | #if IR_TX_ENABLE==1 |
266 | #if IR_TX_ENABLE==1 |
| - | 267 | // TODO: hardcoded to 3 channels?? /jm |
|
| 266 | irTxChannel[0].timerNum=sns_irTransceive_TX0_REPEATE_TIMER; |
268 | irTxChannel[0].timerNum=sns_irTransceive_TX0_REPEATE_TIMER; |
| 267 | irTxChannel[1].timerNum=sns_irTransceive_TX1_REPEATE_TIMER; |
269 | irTxChannel[1].timerNum=sns_irTransceive_TX1_REPEATE_TIMER; |
| 268 | irTxChannel[2].timerNum=sns_irTransceive_TX2_REPEATE_TIMER; |
270 | irTxChannel[2].timerNum=sns_irTransceive_TX2_REPEATE_TIMER; |
| 269 | #endif |
271 | #endif |
| 270 | 272 | ||
| Line 513... | Line 515... | ||
| 513 | rxMsg->Header.ModuleId == sns_irTransceive_ID) |
515 | rxMsg->Header.ModuleId == sns_irTransceive_ID) |
| 514 | { |
516 | { |
| 515 | uint8_t channel; |
517 | uint8_t channel; |
| 516 | switch (rxMsg->Header.Command) |
518 | switch (rxMsg->Header.Command) |
| 517 | { |
519 | { |
| - | 520 | #if IR_TX_ENABLE==1 |
|
| 518 | case CAN_MODULE_CMD_PHYSICAL_IR: |
521 | case CAN_MODULE_CMD_PHYSICAL_IR: |
| 519 | channel = rxMsg->Data[0]>>4; |
522 | channel = rxMsg->Data[0]>>4; |
| 520 | if ((0xf&rxMsg->Data[0]) == CAN_MODULE_ENUM_PHYSICAL_IR_STATUS_PRESSED && channel < IR_SUPPORTED_NUM_CHANNELS) |
523 | if ((0xf&rxMsg->Data[0]) == CAN_MODULE_ENUM_PHYSICAL_IR_STATUS_PRESSED && channel < IR_SUPPORTED_NUM_CHANNELS) |
| 521 | { |
524 | { |
| 522 | if (irTxChannel[channel].state == sns_irTransceive_STATE_IDLE) |
525 | if (irTxChannel[channel].state == sns_irTransceive_STATE_IDLE) |
| 523 | { |
526 | { |
| 524 | irTxChannel[channel].proto.protocol = rxMsg->Data[1]; |
527 | irTxChannel[channel].proto.protocol = rxMsg->Data[1]; |
| 525 | 528 | ||
| 526 | irTxChannel[channel].proto.data = rxMsg->Data[2]; |
529 | irTxChannel[channel].proto.data = rxMsg->Data[2]; |
| 527 | irTxChannel[channel].proto.data = irTxChannel[channel].proto.data<<8; |
530 | irTxChannel[channel].proto.data = irTxChannel[channel].proto.data<<8; |
| 528 | irTxChannel[channel].proto.data |= rxMsg->Data[3]; |
531 | irTxChannel[channel].proto.data |= rxMsg->Data[3]; |
| 529 | irTxChannel[channel].proto.data = irTxChannel[channel].proto.data<<8; |
532 | irTxChannel[channel].proto.data = irTxChannel[channel].proto.data<<8; |
| 530 | irTxChannel[channel].proto.data |= rxMsg->Data[4]; |
533 | irTxChannel[channel].proto.data |= rxMsg->Data[4]; |
| Line 535... | Line 538... | ||
| 535 | } |
538 | } |
| 536 | } |
539 | } |
| 537 | else if ((0xf&rxMsg->Data[0]) == CAN_MODULE_ENUM_PHYSICAL_IR_STATUS_RELEASED && channel < IR_SUPPORTED_NUM_CHANNELS) |
540 | else if ((0xf&rxMsg->Data[0]) == CAN_MODULE_ENUM_PHYSICAL_IR_STATUS_RELEASED && channel < IR_SUPPORTED_NUM_CHANNELS) |
| 538 | { |
541 | { |
| 539 | if (irTxChannel[channel].state != sns_irTransceive_STATE_IDLE) |
542 | if (irTxChannel[channel].state != sns_irTransceive_STATE_IDLE) |
| 540 | { |
543 | { |
| 541 | irTxChannel[channel].stopSend = TRUE; |
544 | irTxChannel[channel].stopSend = TRUE; |
| 542 | } |
545 | } |
| 543 | } |
546 | } |
| 544 | break; |
547 | break; |
| - | 548 | #endif |
|
| 545 | 549 | ||
| 546 | case CAN_MODULE_CMD_IRTRANSCEIVE_IRCONFIG: |
550 | case CAN_MODULE_CMD_IRTRANSCEIVE_IRCONFIG: |
| 547 | channel = rxMsg->Data[0]>>4; |
551 | channel = rxMsg->Data[0]>>4; |
| 548 | uint8_t config = rxMsg->Data[0] & 0x0f; |
552 | uint8_t config = rxMsg->Data[0] & 0x0f; |
| 549 | uint8_t power = rxMsg->Data[1]>>6; |
553 | uint8_t power = rxMsg->Data[1]>>6; |
| Line 564... | Line 568... | ||
| 564 | eeprom_write_byte_crc(EEDATA.ch1_txpower, power, WITHOUT_CRC); |
568 | eeprom_write_byte_crc(EEDATA.ch1_txpower, power, WITHOUT_CRC); |
| 565 | break; |
569 | break; |
| 566 | case 2: |
570 | case 2: |
| 567 | eeprom_write_byte_crc(EEDATA.ch2_config, config, WITHOUT_CRC); |
571 | eeprom_write_byte_crc(EEDATA.ch2_config, config, WITHOUT_CRC); |
| 568 | eeprom_write_byte_crc(EEDATA.ch2_txpower, power, WITHOUT_CRC); |
572 | eeprom_write_byte_crc(EEDATA.ch2_txpower, power, WITHOUT_CRC); |
| 569 | break; |
573 | break; |
| 570 | default: |
574 | default: |
| 571 | break; |
575 | break; |
| 572 | } |
576 | } |
| 573 | EEDATA_UPDATE_CRC; |
577 | EEDATA_UPDATE_CRC; |
| 574 | } |
578 | } |
| 575 | #endif |
579 | #endif |
| 576 | break; |
580 | break; |
| - | 581 | ||
| - | 582 | default: |
|
| - | 583 | break; |
|
| - | 584 | ||
| 577 | } |
585 | } |
| 578 | } |
586 | } |
| 579 | } |
587 | } |
| 580 | 588 | ||
| 581 | void sns_irTransceive_List(uint8_t ModuleSequenceNumber) |
589 | void sns_irTransceive_List(uint8_t ModuleSequenceNumber) |