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| Rev 1813 | Rev 1814 | ||
|---|---|---|---|
| Line 21... | Line 21... | ||
| 21 | #endif |
21 | #endif |
| 22 | 22 | ||
| 23 | #if IR_RX_ENABLE==1 |
23 | #if IR_RX_ENABLE==1 |
| 24 | struct { |
24 | struct { |
| 25 | uint8_t state; |
25 | uint8_t state; |
| - | 26 | uint8_t modfreq; |
|
| 26 | uint16_t *rxbuf; |
27 | uint16_t *rxbuf; |
| 27 | uint8_t rxlen; |
28 | uint8_t rxlen; |
| 28 | uint8_t timerNum; |
29 | uint8_t timerNum; |
| 29 | Ir_Protocol_Data_t proto; |
30 | Ir_Protocol_Data_t proto; |
| 30 | uint8_t newData; |
31 | uint8_t newData; |
| Line 32... | Line 33... | ||
| 32 | #endif |
33 | #endif |
| 33 | 34 | ||
| 34 | #if IR_TX_ENABLE==1 |
35 | #if IR_TX_ENABLE==1 |
| 35 | struct { |
36 | struct { |
| 36 | uint8_t state; |
37 | uint8_t state; |
| - | 38 | uint8_t modfreq; |
|
| 37 | uint16_t *txbuf; |
39 | uint16_t *txbuf; |
| 38 | uint8_t txlen; |
40 | uint8_t txlen; |
| 39 | uint8_t timerNum; |
41 | uint8_t timerNum; |
| 40 | uint8_t repeatCount; |
42 | uint8_t repeatCount; |
| 41 | Ir_Protocol_Data_t proto; |
43 | Ir_Protocol_Data_t proto; |
| Line 92... | Line 94... | ||
| 92 | #endif |
94 | #endif |
| 93 | 95 | ||
| 94 | #ifndef sns_irTransceive_PRONTO_SUPPORT |
96 | #ifndef sns_irTransceive_PRONTO_SUPPORT |
| 95 | #define sns_irTransceive_PRONTO_SUPPORT 0 |
97 | #define sns_irTransceive_PRONTO_SUPPORT 0 |
| 96 | #endif |
98 | #endif |
| - | 99 | ||
| 97 | #if sns_irTransceive_PRONTO_SUPPORT==1 |
100 | #if sns_irTransceive_PRONTO_SUPPORT==1 |
| 98 | #define |
101 | #define sns_irTransceive_BaseFrq (4145146ULL) |
| 99 | /* TODO configurable divider parameter */ |
- | |
| 100 | #define wFrqDiv (0x6d) |
- | |
| 101 | #define divider (1000000ULL*wFrqDiv/BaseFrq) |
- | |
| 102 | - | ||
| 103 | - | ||
| 104 | void send_pronto(uint16_t *buffer, uint8_t len) { |
102 | void send_pronto(uint16_t *buffer, uint8_t len, uint8_t channel, uint8_t modfreq) { |
| 105 | StdCan_Msg_t msg; |
103 | StdCan_Msg_t msg; |
| 106 | 104 | ||
| 107 | StdCan_Set_class(msg.Header, CAN_MODULE_CLASS_SNS); |
105 | StdCan_Set_class(msg.Header, CAN_MODULE_CLASS_SNS); |
| 108 | StdCan_Set_direction(msg.Header, DIRECTIONFLAG_FROM_OWNER); |
106 | StdCan_Set_direction(msg.Header, DIRECTIONFLAG_FROM_OWNER); |
| 109 | msg.Length = 8; |
107 | msg.Length = 8; |
| 110 | msg.Header.ModuleType = CAN_MODULE_TYPE_SNS_IRTRANSCEIVE; |
108 | msg.Header.ModuleType = CAN_MODULE_TYPE_SNS_IRTRANSCEIVE; |
| 111 | msg.Header.ModuleId = sns_irTransceive_ID; |
109 | msg.Header.ModuleId = sns_irTransceive_ID; |
| 112 | msg.Header.Command = CAN_MODULE_CMD_IRTRANSCEIVE_IRPRONTOSTART; |
110 | msg.Header.Command = CAN_MODULE_CMD_IRTRANSCEIVE_IRPRONTOSTART; |
| 113 | 111 | ||
| 114 | msg.Data[0] = 0x00; /* Prontoformat 0x0000 */ |
112 | msg.Data[0] = 0x00; /* Prontoformat 0x0000 */ |
| 115 | msg.Data[1] = 0x00; |
113 | msg.Data[1] = 0x00; |
| 116 | msg.Data[2] = 0x00; /* Freq |
114 | msg.Data[2] = 0x00; /* Freq divider */ |
| 117 | msg.Data[3] = |
115 | msg.Data[3] = modfreq; |
| 118 | msg.Data[4] = 0x00; /* Once seq length, first byte always 0 */ |
116 | msg.Data[4] = 0x00; /* Once seq length, first byte always 0 */ |
| 119 | msg.Data[5] = 0x00; //len/2; /* not correct if any byte overflows */ |
117 | msg.Data[5] = 0x00; //len/2; /* not correct if any byte overflows */ |
| 120 | msg.Data[6] = 0x00; /* Repeat seq length, always 0 for ir receive */ |
118 | msg.Data[6] = 0x00; /* Repeat seq length, always 0 for ir receive */ |
| 121 | msg.Data[7] = 0x00; |
119 | msg.Data[7] = 0x00; |
| 122 | 120 | ||
| 123 | while (StdCan_Put(&msg) != StdCan_Ret_OK) {} |
121 | while (StdCan_Put(&msg) != StdCan_Ret_OK) {} |
| 124 | _delay_ms(1); |
122 | _delay_ms(1); |
| 125 | 123 | ||
| - | 124 | uint16_t divider = (1000000ULL*modfreq/sns_irTransceive_BaseFrq); |
|
| 126 | msg.Header.Command = CAN_MODULE_CMD_IRTRANSCEIVE_IRPRONTODATA1; |
125 | msg.Header.Command = CAN_MODULE_CMD_IRTRANSCEIVE_IRPRONTODATA1; |
| 127 | /* Counter for buffer */ |
126 | /* Counter for buffer */ |
| 128 | uint8_t i = 0; |
127 | uint8_t i = 0; |
| 129 | /* Counter for filling can frame data */ |
128 | /* Counter for filling can frame data */ |
| 130 | uint8_t j = 0; |
129 | uint8_t j = 0; |
| Line 139... | Line 138... | ||
| 139 | /* Clear memory */ |
138 | /* Clear memory */ |
| 140 | mem = 0; |
139 | mem = 0; |
| 141 | } |
140 | } |
| 142 | else |
141 | else |
| 143 | { |
142 | { |
| - | 143 | uint16_t data = buffer[i]/divider; |
|
| 144 | if ( |
144 | if (data >= (2^8)) |
| 145 | { |
145 | { |
| 146 | /* If data does not fit into 8 bit, then split, memorize low byte */ |
146 | /* If data does not fit into 8 bit, then split, memorize low byte */ |
| 147 | mem = |
147 | mem = data&0xff; |
| 148 | /* Buffer high byte */ |
148 | /* Buffer high byte */ |
| 149 | msg.Data[j] = ( |
149 | msg.Data[j] = (data>>8)&0xff; |
| 150 | j++; |
150 | j++; |
| 151 | if (j==8) |
151 | if (j==8) |
| 152 | { |
152 | { |
| 153 | /* If send buffer is full, send frame */ |
153 | /* If send buffer is full, send frame */ |
| 154 | /* can buffers will be filled when sending more than 2-3 messages, so retry until sent */ |
154 | /* can buffers will be filled when sending more than 2-3 messages, so retry until sent */ |
| Line 156... | Line 156... | ||
| 156 | _delay_ms(1); |
156 | _delay_ms(1); |
| 157 | j=0; |
157 | j=0; |
| 158 | msg.Header.Command++; |
158 | msg.Header.Command++; |
| 159 | } |
159 | } |
| 160 | /* Set complementary burst pair to 0 to indicate 16bit transmission */ |
160 | /* Set complementary burst pair to 0 to indicate 16bit transmission */ |
| 161 | msg.Data[j] = 0; |
161 | msg.Data[j] = 0; |
| 162 | } |
162 | } |
| 163 | else |
163 | else |
| 164 | { |
164 | { |
| 165 | msg.Data[j] = |
165 | msg.Data[j] = data&0xff; |
| 166 | } |
166 | } |
| 167 | 167 | ||
| 168 | i++; |
168 | i++; |
| 169 | } |
169 | } |
| 170 | 170 | ||
| 171 | j++; |
171 | j++; |
| 172 | if (j==8) |
172 | if (j==8) |
| 173 | { |
173 | { |
| Line 175... | Line 175... | ||
| 175 | /* can buffers will be filled when sending more than 2-3 messages, so retry until sent */ |
175 | /* can buffers will be filled when sending more than 2-3 messages, so retry until sent */ |
| 176 | while (StdCan_Put(&msg) != StdCan_Ret_OK) {} |
176 | while (StdCan_Put(&msg) != StdCan_Ret_OK) {} |
| 177 | _delay_ms(1); |
177 | _delay_ms(1); |
| 178 | j=0; |
178 | j=0; |
| 179 | msg.Header.Command++; |
179 | msg.Header.Command++; |
| 180 | } |
180 | } |
| 181 | 181 | ||
| 182 | } |
182 | } |
| 183 | 183 | ||
| 184 | /* msg command kept from for loop, but increase 16 to send ProntoEnd */ |
184 | /* msg command kept from for loop, but increase 16 to send ProntoEnd */ |
| 185 | msg.Header.Command+=16; |
185 | msg.Header.Command+=16; |
| 186 | msg.Length = j; |
186 | msg.Length = j; |
| 187 | /* data kept from loop */ |
187 | /* data kept from loop */ |
| Line 189... | Line 189... | ||
| 189 | while (StdCan_Put(&msg) != StdCan_Ret_OK) {} |
189 | while (StdCan_Put(&msg) != StdCan_Ret_OK) {} |
| 190 | _delay_ms(1); |
190 | _delay_ms(1); |
| 191 | } |
191 | } |
| 192 | #endif |
192 | #endif |
| 193 | 193 | ||
| 194 | 194 | ||
| 195 | #if IR_RX_ENABLE==1 |
195 | #if IR_RX_ENABLE==1 |
| 196 | void sns_irTransceive_RX_done_callback(uint8_t channel, uint16_t *buffer, uint8_t len) |
196 | void sns_irTransceive_RX_done_callback(uint8_t channel, uint16_t *buffer, uint8_t len) |
| 197 | { |
197 | { |
| 198 | if (channel < IR_SUPPORTED_NUM_CHANNELS) |
198 | if (channel < IR_SUPPORTED_NUM_CHANNELS) |
| 199 | { |
199 | { |
| 200 | irRxChannel[channel].newData = TRUE; |
200 | irRxChannel[channel].newData = TRUE; |
| 201 | irRxChannel[channel].rxlen = len; |
201 | irRxChannel[channel].rxlen = len; |
| 202 | } |
202 | } |
| 203 | } |
203 | } |
| 204 | #endif |
204 | #endif |
| 205 | 205 | ||
| 206 | 206 | ||
| 207 | #if IR_TX_ENABLE==1 |
207 | #if IR_TX_ENABLE==1 |
| 208 | void sns_irTransceive_TX_done_callback(uint8_t channel) |
208 | void sns_irTransceive_TX_done_callback(uint8_t channel) |
| 209 | { |
209 | { |
| 210 | if (channel < IR_SUPPORTED_NUM_CHANNELS) |
210 | if (channel < IR_SUPPORTED_NUM_CHANNELS) |
| 211 | { |
211 | { |
| 212 | irTxChannel[channel].sendComplete = TRUE; |
212 | irTxChannel[channel].sendComplete = TRUE; |
| 213 | } |
213 | } |
| 214 | } |
214 | } |
| 215 | #endif |
215 | #endif |
| 216 | 216 | ||
| 217 | 217 | ||
| 218 | void sns_irTransceive_setConfig(uint8_t channel, uint8_t config, uint8_t power) |
218 | void sns_irTransceive_setConfig(uint8_t channel, uint8_t config, uint8_t power, uint8_t modfreq) |
| 219 | { |
219 | { |
| 220 | if (channel < IR_SUPPORTED_NUM_CHANNELS && config <= CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE && power < 4) |
220 | if (channel < IR_SUPPORTED_NUM_CHANNELS && config <= CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE && power < 4) |
| 221 | { |
221 | { |
| 222 | #if IR_RX_ENABLE==1 |
222 | #if IR_RX_ENABLE==1 |
| 223 | if (config == CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE) |
223 | if (config == CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE) |
| 224 | { |
224 | { |
| 225 | #if IR_TX_ENABLE==1 |
225 | #if IR_TX_ENABLE==1 |
| 226 | irTxChannel[channel].state = sns_irTransceive_STATE_DISABLED; |
226 | irTxChannel[channel].state = sns_irTransceive_STATE_DISABLED; |
| 227 | #endif |
227 | #endif |
| - | 228 | irRxChannel[channel].modfreq = modfreq; |
|
| 228 | irRxChannel[channel].rxbuf = buf[channel]; |
229 | irRxChannel[channel].rxbuf = buf[channel]; |
| 229 | switch (channel) |
230 | switch (channel) |
| 230 | { |
231 | { |
| 231 | case 0: |
232 | case 0: |
| 232 | gpio_clr_pin(sns_irTransceive_VCC_EN0_PIN); |
233 | gpio_clr_pin(sns_irTransceive_VCC_EN0_PIN); |
| Line 249... | Line 250... | ||
| 249 | if (config == CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_TRANSMIT) |
250 | if (config == CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_TRANSMIT) |
| 250 | { |
251 | { |
| 251 | #if IR_RX_ENABLE==1 |
252 | #if IR_RX_ENABLE==1 |
| 252 | irRxChannel[channel].state = sns_irTransceive_STATE_DISABLED; |
253 | irRxChannel[channel].state = sns_irTransceive_STATE_DISABLED; |
| 253 | #endif |
254 | #endif |
| 254 | 255 | irTxChannel[channel].modfreq = modfreq; |
|
| 255 | irTxChannel[channel].txbuf = buf[channel]; |
256 | irTxChannel[channel].txbuf = buf[channel]; |
| 256 | switch (channel) |
257 | switch (channel) |
| 257 | { |
258 | { |
| 258 | case 0: |
259 | case 0: |
| 259 | #if IR_RX_ENABLE==1 |
260 | #if IR_RX_ENABLE==1 |
| Line 413... | Line 414... | ||
| 413 | 414 | ||
| 414 | #ifdef sns_irTransceive_USEEEPROM |
415 | #ifdef sns_irTransceive_USEEEPROM |
| 415 | if (EEDATA_OK) |
416 | if (EEDATA_OK) |
| 416 | { |
417 | { |
| 417 | /* Use stored data to set initial values for the module */ |
418 | /* Use stored data to set initial values for the module */ |
| 418 | sns_irTransceive_setConfig(0, eeprom_read_byte(EEDATA.ch0_config), eeprom_read_byte(EEDATA.ch0_txpower)); |
419 | sns_irTransceive_setConfig(0, eeprom_read_byte(EEDATA.ch0_config), eeprom_read_byte(EEDATA.ch0_txpower), eeprom_read_byte(EEDATA.ch0_modfreq)); |
| 419 | sns_irTransceive_setConfig(1, eeprom_read_byte(EEDATA.ch1_config), eeprom_read_byte(EEDATA.ch1_txpower)); |
420 | sns_irTransceive_setConfig(1, eeprom_read_byte(EEDATA.ch1_config), eeprom_read_byte(EEDATA.ch1_txpower), eeprom_read_byte(EEDATA.ch1_modfreq)); |
| 420 | sns_irTransceive_setConfig(2, eeprom_read_byte(EEDATA.ch2_config), eeprom_read_byte(EEDATA.ch2_txpower)); |
421 | sns_irTransceive_setConfig(2, eeprom_read_byte(EEDATA.ch2_config), eeprom_read_byte(EEDATA.ch2_txpower), eeprom_read_byte(EEDATA.ch2_modfreq)); |
| 421 | } |
422 | } |
| 422 | else |
423 | else |
| 423 | { |
424 | { |
| 424 | /* The CRC of the EEPROM is not correct, store default values and update CRC */ |
425 | /* The CRC of the EEPROM is not correct, store default values and update CRC */ |
| 425 | eeprom_write_byte_crc(EEDATA.ch0_config, CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, WITHOUT_CRC); |
426 | eeprom_write_byte_crc(EEDATA.ch0_config, CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, WITHOUT_CRC); |
| 426 | eeprom_write_byte_crc(EEDATA.ch0_txpower, 0, WITHOUT_CRC); |
427 | eeprom_write_byte_crc(EEDATA.ch0_txpower, 0, WITHOUT_CRC); |
| - | 428 | eeprom_write_byte_crc(EEDATA.ch0_modfreq, BaseFrq/38000, WITHOUT_CRC); |
|
| 427 | eeprom_write_byte_crc(EEDATA.ch1_config, CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, WITHOUT_CRC); |
429 | eeprom_write_byte_crc(EEDATA.ch1_config, CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, WITHOUT_CRC); |
| 428 | eeprom_write_byte_crc(EEDATA.ch1_txpower, 0, WITHOUT_CRC); |
430 | eeprom_write_byte_crc(EEDATA.ch1_txpower, 0, WITHOUT_CRC); |
| - | 431 | eeprom_write_byte_crc(EEDATA.ch1_modfreq, BaseFrq/38000, WITHOUT_CRC); |
|
| 429 | eeprom_write_byte_crc(EEDATA.ch2_config, CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, WITHOUT_CRC); |
432 | eeprom_write_byte_crc(EEDATA.ch2_config, CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_AUTO, WITHOUT_CRC); |
| 430 | eeprom_write_byte_crc(EEDATA.ch2_txpower, 0, WITHOUT_CRC); |
433 | eeprom_write_byte_crc(EEDATA.ch2_txpower, 0, WITHOUT_CRC); |
| - | 434 | eeprom_write_byte_crc(EEDATA.ch2_modfreq, BaseFrq/38000, WITHOUT_CRC); |
|
| 431 | EEDATA_UPDATE_CRC; |
435 | EEDATA_UPDATE_CRC; |
| 432 | } |
436 | } |
| 433 | #endif |
437 | #endif |
| 434 | } |
438 | } |
| 435 | 439 | ||
| Line 480... | Line 484... | ||
| 480 | #if sns_irTransceive_PRONTO_SUPPORT==0 |
484 | #if sns_irTransceive_PRONTO_SUPPORT==0 |
| 481 | send_debug(irRxChannel[channel].rxbuf, irRxChannel[channel].rxlen); |
485 | send_debug(irRxChannel[channel].rxbuf, irRxChannel[channel].rxlen); |
| 482 | irRxChannel[channel].proto.timeout=300; |
486 | irRxChannel[channel].proto.timeout=300; |
| 483 | #endif |
487 | #endif |
| 484 | #if sns_irTransceive_PRONTO_SUPPORT==1 |
488 | #if sns_irTransceive_PRONTO_SUPPORT==1 |
| 485 | send_pronto(irRxChannel[channel].rxbuf, irRxChannel[channel].rxlen); |
489 | send_pronto(irRxChannel[channel].rxbuf, irRxChannel[channel].rxlen, channel, irRxChannel[channel].modfreq); |
| 486 | irRxChannel[channel].proto.timeout=300; |
490 | irRxChannel[channel].proto.timeout=300; |
| 487 | #endif |
491 | #endif |
| 488 | 492 | ||
| 489 | #endif |
493 | #endif |
| 490 | } |
494 | } |
| Line 656... | Line 660... | ||
| 656 | 660 | ||
| 657 | case CAN_MODULE_CMD_IRTRANSCEIVE_IRCONFIG: |
661 | case CAN_MODULE_CMD_IRTRANSCEIVE_IRCONFIG: |
| 658 | channel = rxMsg->Data[0]>>4; |
662 | channel = rxMsg->Data[0]>>4; |
| 659 | uint8_t config = rxMsg->Data[0] & 0x0f; |
663 | uint8_t config = rxMsg->Data[0] & 0x0f; |
| 660 | uint8_t power = rxMsg->Data[1]>>6; |
664 | uint8_t power = rxMsg->Data[1]>>6; |
| - | 665 | uint8_t modfreq = rxMsg->Data[2]; |
|
| 661 | 666 | ||
| 662 | sns_irTransceive_setConfig(channel, config, power); |
667 | sns_irTransceive_setConfig(channel, config, power, modfreq); |
| 663 | 668 | ||
| 664 | #ifdef sns_irTransceive_USEEEPROM |
669 | #ifdef sns_irTransceive_USEEEPROM |
| 665 | if (channel < IR_SUPPORTED_NUM_CHANNELS && config <= CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE && power < 4) |
670 | if (channel < IR_SUPPORTED_NUM_CHANNELS && config <= CAN_MODULE_ENUM_IRTRANSCEIVE_IRCONFIG_DIRECTION_RECEIVE && power < 4) |
| 666 | { |
671 | { |
| 667 | switch (channel) |
672 | switch (channel) |
| 668 | { |
673 | { |
| 669 | case 0: |
674 | case 0: |
| 670 | eeprom_write_byte_crc(EEDATA.ch0_config, config, WITHOUT_CRC); |
675 | eeprom_write_byte_crc(EEDATA.ch0_config, config, WITHOUT_CRC); |
| 671 | eeprom_write_byte_crc(EEDATA.ch0_txpower, power, WITHOUT_CRC); |
676 | eeprom_write_byte_crc(EEDATA.ch0_txpower, power, WITHOUT_CRC); |
| - | 677 | eeprom_write_byte_crc(EEDATA.ch0_modfreq, modfreq, WITHOUT_CRC); |
|
| 672 | break; |
678 | break; |
| 673 | case 1: |
679 | case 1: |
| 674 | eeprom_write_byte_crc(EEDATA.ch1_config, config, WITHOUT_CRC); |
680 | eeprom_write_byte_crc(EEDATA.ch1_config, config, WITHOUT_CRC); |
| 675 | eeprom_write_byte_crc(EEDATA.ch1_txpower, power, WITHOUT_CRC); |
681 | eeprom_write_byte_crc(EEDATA.ch1_txpower, power, WITHOUT_CRC); |
| - | 682 | eeprom_write_byte_crc(EEDATA.ch1_modfreq, modfreq, WITHOUT_CRC); |
|
| 676 | break; |
683 | break; |
| 677 | case 2: |
684 | case 2: |
| 678 | eeprom_write_byte_crc(EEDATA.ch2_config, config, WITHOUT_CRC); |
685 | eeprom_write_byte_crc(EEDATA.ch2_config, config, WITHOUT_CRC); |
| 679 | eeprom_write_byte_crc(EEDATA.ch2_txpower, power, WITHOUT_CRC); |
686 | eeprom_write_byte_crc(EEDATA.ch2_txpower, power, WITHOUT_CRC); |
| - | 687 | eeprom_write_byte_crc(EEDATA.ch2_modfreq, modfreq, WITHOUT_CRC); |
|
| 680 | break; |
688 | break; |
| 681 | default: |
689 | default: |
| 682 | break; |
690 | break; |
| 683 | } |
691 | } |
| 684 | EEDATA_UPDATE_CRC; |
692 | EEDATA_UPDATE_CRC; |