Subversion Repositories HomeAutomation

Rev

Rev 664 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | SVN | RSS feed

Rev 664 Rev 680
Line 13... Line 13...
13 
#define MCP_CAN_BITRATE_KBPS    250
 13 
#define MCP_CAN_BITRATE_KBPS    250
14 
#define MCP_CLOCK_FREQ_MHZ      20
 14 
#define MCP_CLOCK_FREQ_MHZ      20
15 
#define MCP_CLOCK_PRESC         1
 15 
#define MCP_CLOCK_PRESC         1
16 
 
 16 
 
17 
 
 17 
 
18 
//#define ENC28J60_USART_SPI_MODE
 18 
#define ENC28J60_USART_SPI_MODE
- 
 
 19 
 
- 
 
 20 
 /*
- 
 
 21 
 * mac and ip have to be unique in your local area network.
- 
 
 22 
 * You can not have the same numbers in two devices:
- 
 
 23 
 */
- 
 
 24 
 
- 
 
 25 
#define ENC28J60_MAC1           0x54
- 
 
 26 
#define ENC28J60_MAC2           0x55
- 
 
 27 
#define ENC28J60_MAC3           0x58
- 
 
 28 
#define ENC28J60_MAC4           0x10
- 
 
 29 
#define ENC28J60_MAC5           0x00
- 
 
 30 
#define ENC28J60_MAC6           0x27
- 
 
 31 
 
- 
 
 32 
#define ENC28J60_IP1            192
- 
 
 33 
#define ENC28J60_IP2            168
- 
 
 34 
#define ENC28J60_IP3            0
- 
 
 35 
#define ENC28J60_IP4            50
19 
 
 36 
 
20 
 /**
 37 
 /**
21 
 * ENC28J60 Chip Select port on avr.
 38 
 * ENC28J60 Chip Select port on avr.
22 
 */
 39 
 */
23 
 
 40 
 
24 
#define ENC28J60_CS_PORT    PORTC
 41 
#define ENC28J60_CS_PORT    PORTC
25 
#define ENC28J60_CS_DDR     DDRC
 42 
#define ENC28J60_CS_DDR     DDRC
26 
#define ENC28J60_CS         0
 43 
#define ENC28J60_CS         PC0
27 
 
 44 
 
28 
 /**
 45 
 /**
29 
 * ENC28J60 Reset port on avr.
 46 
 * ENC28J60 Reset port on avr.
30 
 */
 47 
 */
31 
 
 - 
 
32 
#define ENC28J60_RESET_PORT PORTC
 48 
#define ENC28J60_RESET_PORT PORTC
33 
#define ENC28J60_RESET_DDR  DDRC
 49 
#define ENC28J60_RESET_DDR  DDRC
34 
#define ENC28J60_RESET  1
 50 
#define ENC28J60_RESET      PC1
35 
 
 51 
 
36 
// only for USART in SPImode
 52 
// only for USART in SPImode
37 
#define XCK_DDR             DDRD
 53 
#define XCK_DDR             DDRD
38 
#define XCK                 PD4
 54 
#define XCK                 PD4
39 
 
 55