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| 2 | * |
2 | * |
| 3 | * CAN driver |
3 | * CAN driver |
| 4 | * |
4 | * |
| 5 | ********************************************************************* |
5 | ********************************************************************* |
| 6 | * FileName: $HeadURL: https://svn.auml.se/svn/HomeAutomation/trunk/EmbeddedSoftware/PIC/canToSerial/Source/CAN.c $ |
6 | * FileName: $HeadURL: https://svn.auml.se/svn/HomeAutomation/trunk/EmbeddedSoftware/PIC/canToSerial/Source/CAN.c $ |
| 7 | * Last changed: $LastChangedDate: |
7 | * Last changed: $LastChangedDate: 2007-01-28 14:58:11 +0100 (Sun, 28 Jan 2007) $ |
| 8 | * By: $LastChangedBy: johboh $ |
8 | * By: $LastChangedBy: johboh $ |
| 9 | * Revision: $Revision: |
9 | * Revision: $Revision: 260 $ |
| 10 | ********************************************************************/ |
10 | ********************************************************************/ |
| 11 | 11 | ||
| 12 | #include <CANdefs.h> |
12 | #include <CANdefs.h> |
| 13 | #include <stackTasks.h> |
13 | #include <stackTasks.h> |
| 14 | #include <CAN.h> |
14 | #include <CAN.h> |
| Line 32... | Line 32... | ||
| 32 | CANCON = 0x80; //request config mode |
32 | CANCON = 0x80; //request config mode |
| 33 | while ((CANSTAT & 0xE0) != 0x80 ); //wait for config mode request |
33 | while ((CANSTAT & 0xE0) != 0x80 ); //wait for config mode request |
| 34 | 34 | ||
| 35 | // BAUD AND TQS |
35 | // BAUD AND TQS |
| 36 | 36 | ||
| - | 37 | //BRGCON1 = 0x03; //500Kbit@40MHz 1TQ Sync, 2TQ Prop, 4TQ Phase1, 3TQ Phase2 |
|
| - | 38 | //BRGCON2 = 0x99; |
|
| - | 39 | //BRGCON3 = 0x02; |
|
| - | 40 | ||
| - | 41 | //75%, 250Kbps @40MHz |
|
| - | 42 | //BRGCON1 = 0x09; |
|
| - | 43 | //BRGCON2 = 0xDB; |
|
| - | 44 | //BRGCON3 = 0x01; |
|
| - | 45 | ||
| - | 46 | //75% ,1 , 500Kbps @40MHz |
|
| - | 47 | //BRGCON1 = 0x01; |
|
| - | 48 | //BRGCON2 = (0xB6 | 0x80); |
|
| - | 49 | //BRGCON3 = 0x04; |
|
| - | 50 | ||
| - | 51 | //75% ,1 , 500Kbps @80MHz |
|
| - | 52 | //BRGCON1 = 0x03; |
|
| - | 53 | //BRGCON2 = (0xB6 | 0x80); |
|
| - | 54 | //BRGCON3 = 0x04; |
|
| - | 55 | ||
| - | 56 | // 500Khz@40Mhz (new by the book) |
|
| - | 57 | BRGCON1 = 0x04; |
|
| - | 58 | BRGCON2 = 0xD1; |
|
| - | 59 | BRGCON3 = 0x81; |
|
| - | 60 | ||
| - | 61 | ||
| 37 |
|
62 | //BRGCON1=0; |
| 38 | 63 | ||
| 39 | // Sync_Seq = 2 x TQ = 1 |
64 | // Sync_Seq = 2 x TQ = 1 |
| 40 | BRGCON1bits. |
65 | //BRGCON1bits.SJW1=0; |
| 41 | BRGCON1bits. |
66 | //BRGCON1bits.SJW0=1; |
| 42 | 67 | ||
| 43 | // Setting BRP. |
68 | // Setting BRP. |
| 44 |
|
69 | //BRGCON1=BRGCON1|CAN_BRP; |
| 45 | 70 | ||
| 46 | // Maximum PHEG1 |
71 | // Maximum PHEG1 |
| 47 | BRGCON2bits. |
72 | //BRGCON2bits.SEG2PHTS = 1; |
| 48 | 73 | ||
| 49 | // Phase_Seg1 = 2 x TQ = 1 |
74 | // Phase_Seg1 = 2 x TQ = 1 |
| 50 | BRGCON2bits. |
75 | //BRGCON2bits.SEG1PH2 = 0; |
| 51 | BRGCON2bits. |
76 | //BRGCON2bits.SEG1PH1 = 0; |
| 52 | BRGCON2bits. |
77 | //BRGCON2bits.SEG1PH0 = 1; |
| 53 | 78 | ||
| 54 | // Prop_Seq = 2 x TQ = 1 |
79 | // Prop_Seq = 2 x TQ = 1 |
| 55 | BRGCON2bits. |
80 | //BRGCON2bits.PRSEG2 = 0; |
| 56 | BRGCON2bits. |
81 | //BRGCON2bits.PRSEG1 = 0; |
| 57 | BRGCON2bits. |
82 | //BRGCON2bits.PRSEG0 = 1; |
| 58 | 83 | ||
| 59 | // Enableing bus wake-up |
84 | // Enableing bus wake-up |
| 60 | BRGCON3bits. |
85 | //BRGCON3bits.WAKDIS = 0; |
| 61 | 86 | ||
| 62 | // Dont use filter when wakeup |
87 | // Dont use filter when wakeup |
| 63 | BRGCON3bits. |
88 | //BRGCON3bits.WAKFIL = 0; |
| 64 | 89 | ||
| 65 | // Phase_Seg2 = 2 x TQ = 1 |
90 | // Phase_Seg2 = 2 x TQ = 1 |
| 66 | BRGCON3bits. |
91 | //BRGCON3bits.SEG2PH2 = 0; |
| 67 | BRGCON3bits. |
92 | //BRGCON3bits.SEG2PH1 = 0; |
| 68 | BRGCON3bits. |
93 | //BRGCON3bits.SEG2PH0 = 1; |
| 69 | 94 | ||
| 70 | ECANCON=0; |
95 | ECANCON=0; |
| 71 | ECANCONbits.MDSEL1 = 1; |
96 | ECANCONbits.MDSEL1 = 1; |
| 72 | ECANCONbits.MDSEL0 = 0; |
97 | ECANCONbits.MDSEL0 = 0; |
| 73 | 98 | ||
| 74 | 99 | ||
| 75 | // FILTERS AND MASKS |
100 | // FILTERS AND MASKS |
| 76 | RXB0CONbits.RXM1=1; |
101 | RXB0CONbits.RXM1=1; |
| 77 | RXB0CONbits.RXM0=0; |
102 | RXB0CONbits.RXM0=0; |
| 78 | 103 | ||
| - | 104 | // Set ressesive VDD |
|
| - | 105 | CIOCONbits.ENDRHI = 1; |
|
| 79 | 106 | ||
| 80 | // INTERRUPTS |
107 | // INTERRUPTS |
| 81 | 108 | ||
| 82 | // Diable transmit interrupt |
109 | // Diable transmit interrupt |
| 83 | TXBIE = 0; |
110 | TXBIE = 0; |