Subversion Repositories hardware

Version 4
SHEET 1 19580 6792
WIRE 272 -656 272 -704
WIRE 480 -640 528 -704
WIRE 688 -640 608 -704
WIRE 1088 -576 1040 -576
WIRE 1248 -576 1248 -592
WIRE 1248 -576 1088 -576
WIRE 272 -528 272 -576
WIRE 448 -528 272 -528
WIRE 560 -528 560 -560
WIRE 448 -512 448 -528
WIRE 528 -512 448 -512
WIRE 688 -496 688 -640
WIRE 688 -496 592 -496
WIRE 736 -496 688 -496
WIRE 912 -496 816 -496
WIRE 1040 -496 1040 -576
WIRE 1040 -496 912 -496
WIRE 480 -480 480 -640
WIRE 528 -480 480 -480
WIRE 320 -464 320 -480
WIRE 352 -464 320 -464
WIRE 480 -464 480 -480
WIRE 480 -464 432 -464
WIRE 912 -448 912 -496
WIRE 320 -432 320 -464
WIRE 272 -416 272 -528
WIRE 272 -288 272 -336
WIRE 560 -288 560 -464
WIRE 688 -288 560 -288
WIRE 752 -288 688 -288
WIRE 912 -288 912 -368
WIRE 912 -288 752 -288
WIRE 1248 -288 912 -288
WIRE 752 -272 752 -288
WIRE 272 -160 272 -208
WIRE 688 -160 688 -288
WIRE 688 -160 272 -160
WIRE 304 -96 -96 -96
WIRE 400 -96 304 -96
WIRE 576 -96 400 -96
WIRE 640 -96 576 -96
WIRE 960 -96 640 -96
WIRE 640 -64 640 -96
WIRE -96 -16 -96 -96
WIRE 576 0 576 -96
WIRE 1088 16 864 16
WIRE 576 32 576 0
WIRE 640 48 640 0
WIRE 720 48 640 48
WIRE 832 48 800 48
WIRE 400 64 400 -96
WIRE 576 64 576 48
WIRE 640 64 640 48
WIRE 960 80 960 -96
WIRE 576 96 576 64
WIRE 832 96 832 48
WIRE 864 96 832 96
WIRE 928 96 864 96
WIRE 1088 112 1088 16
WIRE 1088 112 992 112
WIRE 1152 112 1088 112
WIRE 864 128 832 128
WIRE 928 128 864 128
WIRE 640 176 640 144
WIRE 720 176 640 176
WIRE 832 176 832 128
WIRE 832 176 800 176
WIRE 576 192 576 176
WIRE 640 192 640 176
WIRE 640 192 576 192
WIRE -608 208 -752 208
WIRE 640 208 640 192
WIRE 1264 208 864 208
WIRE 1344 208 1264 208
WIRE -96 240 -96 64
WIRE -96 240 -112 240
WIRE 1152 272 1152 112
WIRE -752 304 -752 288
WIRE -544 304 -752 304
WIRE 400 304 400 128
WIRE 640 304 640 288
WIRE 640 304 400 304
WIRE -752 320 -752 304
WIRE 96 320 -16 320
WIRE 640 336 640 304
WIRE -16 384 -16 320
WIRE 528 416 496 416
WIRE 592 416 528 416
WIRE -752 544 -752 400
WIRE -112 544 -112 240
WIRE -112 544 -752 544
WIRE -16 544 -16 464
WIRE -16 544 -112 544
WIRE 512 544 512 512
WIRE 512 544 -16 544
WIRE 640 544 640 432
WIRE 640 544 512 544
WIRE 960 544 960 144
WIRE 960 544 640 544
WIRE 1152 544 1152 352
WIRE 1152 544 960 544
WIRE 1456 544 1152 544
FLAG -112 544 0
FLAG 304 -96 Vcc
FLAG 752 -272 0
FLAG 320 -464 Current
FLAG 1152 112 Current
FLAG 1088 -576 Transistor
FLAG 528 416 Transistor
FLAG -544 304 Transistor2
FLAG 96 320 5Volt
FLAG 1264 208 5Volt
FLAG 560 -560 5Volt
FLAG 272 -704 5Volt
FLAG -608 208 5Volt
SYMBOL LED 624 -64 R0
SYMATTR InstName D1
SYMATTR Value LXK2-PW14
SYMBOL ind 624 192 R0
SYMATTR InstName L1
SYMATTR Value 100µ
SYMATTR SpiceLine Ipk=1.25 Rser=0.165 Rpar=9425 Cpar=0 mfg="Coilcraft" pn="MSS1260-104MX"
SYMBOL voltage -96 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR SpiceLine Rser=0.1 Cpar=10u
SYMATTR InstName V1
SYMATTR Value 8
SYMBOL res 624 48 R0
SYMATTR InstName R1
SYMATTR Value 0.1
SYMBOL nmos 592 336 R0
SYMATTR InstName M1
SYMATTR Value Si5902DC
SYMBOL schottky 416 128 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D2
SYMATTR Value B530C
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL voltage -16 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR SpiceLine Rser=0 Cpar=10u
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res -768 192 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage -752 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR SpiceLine Rser=0 Cpar=10u
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 35u 2n 2n 3u 8u 20)
SYMBOL Opamps\\LT1813 1568 32 R0
SYMATTR InstName U1
SYMBOL res 848 0 R0
SYMATTR InstName R3
SYMATTR Value 250k
SYMBOL res 848 112 R0
SYMATTR InstName R4
SYMATTR Value 250k
SYMBOL res 816 160 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value 5k
SYMBOL res 816 32 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R6
SYMATTR Value 5k
SYMBOL res 1136 256 R0
SYMATTR InstName R7
SYMATTR Value 10k
SYMBOL Opamps\\LT1813 1312 -528 R0
SYMATTR InstName U2
SYMBOL res 256 -432 R0
SYMATTR InstName R10
SYMATTR Value 2k
SYMBOL res 448 -480 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R11
SYMATTR Value 1k
SYMBOL res 624 -720 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R12
SYMATTR Value 40k
SYMBOL res 832 -512 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R13
SYMATTR Value 10
SYMBOL res 256 -672 R0
SYMATTR InstName R14
SYMATTR Value 2k
SYMBOL res 896 -464 R0
SYMATTR InstName R8
SYMATTR Value 10k
SYMBOL voltage 272 -304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 132 Left 0
SYMATTR SpiceLine Rser=0 Cpar=10u
SYMATTR InstName V4
SYMATTR Value PULSE(0 5 30u 2n 2n 60u 100u 20)
SYMBOL cap 560 0 R0
SYMATTR InstName C1
SYMATTR Value 50n
SYMATTR SpiceLine V=10 Irms=10.541 Rser=0.004 Lser=0
SYMBOL res 560 80 R0
SYMATTR InstName R9
SYMATTR Value 0.001
SYMBOL Opamps\\opamp2 960 48 R0
SYMATTR InstName U3
SYMATTR Value TLC07X_5V
SYMBOL Opamps\\opamp2 560 -560 R0
SYMATTR InstName U4
SYMATTR Value AD8646
TEXT -128 600 Left 0 !.tran 400u startup
TEXT -144 -248 Left 0 ;Detta är PWM-utgången på AVRen
TEXT 664 -128 Left 0 ;Frekvensen på switchningarna justeras med C1, ett för stort värde på C1 ger dock översväng...
TEXT -16 272 Left 0 ;V2 är 5 volt från corecard
TEXT -784 112 Left 0 ;Används för att styra utan\nregulator, ska alltså ej vara\nmed på expansionen
TEXT 1992 -616 Left 0 !* SPICE simulation model for TLV2371\n*\n* Compatible with PSpice ver. 8.0, Tina Spice V6 and V7\n*\n* Revised May 2009, to correct M48 channel width\n*\n***************************************************************\n*  (C) Copyright 2009 Texas Instruments Incorporated. All rights reserved.  \n***************************************************************\n** This model is designed as an aid for customers of Texas Instruments.     \n** TI and its licensors and suppliers make no warranties, either expressed  \n** or implied, with respect to this model, including the warranties of      \n** merchantability or fitness for a particular purpose. The model is        \n** provided solely on an "as is" basis. The entire risk as to its quality   \n** and performance is with the customer                                            \n***************************************************************\n*\n* BEGIN MODEL TLV2371\n* PINOUT ORDER +IN -IN +V -V OUT\n* PINOUT ORDER  3   4   6  2  1\n.SUBCKT TLV2371 3 4 6 2 1\n* BEGIN NOTES\n* FOR MORE ACCURATE CURRENTS\n* IF LOOKING AT BIAS CURRENT\n* USE GMIN-1E-13\n* MODEL TEMPERATURE RANGE IS\n* -40 C TO +125 C, NOT ALL\n* PARAMETERS TRACK THOSE OF\n* THE REAL PART VS TEMPERATURE\n* END NOTES\n* BEGIN FEATURES\n* OPEN LOOP GAIN AND PHASE\n* INPUT VOLTAGE NOISE W 1/F\n* INPUT CURRENT NOISE\n* INPUT BIAS CURRENT\n* INPUT BIAS CURRENT VS TEMPERATURE\n* INPUT CAPACITANCE\n* INPUT COMMON MODE VOLTAGE RANGE\n* INPUT VOS SHIFT WITH VCM\n* INPUT CLAMPS TO RAILS\n* CMRR WITH FREQUENCY EFFECTS\n* PSRR WITH FREQUENCY EFFECTS\n* SLEW RATE\n* QUIESCENT CURRENT\n* HIGH CLOAD EFFECTS\n* CLASS AB BIAS IN OUTPUT STAGE\n* OUTPUT CURRENT THROUGH SUPPLIES\n* OUTPUT CURRENT LIMITING\n* OUTPUT CLAMPS TO RAILS\n* OUTPUT SWING VS OUTPUT CURRENT\n* END FEATURES\nVEN 5 2 2\nREN 5 2 1E12\nQ20 7 8 9 QLN\nR3 10 11 2\nR4 12 11 2\nR10 8 13 1E3\nR11 14 15 1E3\nR12 16 6 4\nR13 2 17 4\nR16 18 19 200\nR17 20 21 4\nR18 9 22 4\nD5 23 6 DD\nD6 2 23 DD\nD7 24 0 DIN\nD8 25 0 DIN\nI8 0 24 0.1E-3\nI9 0 25 0.1E-3\nE2 9 0 2 0 1\nE3 21 0 6 0 1\nD9 26 0 DVN\nD10 27 0 DVN\nI10 0 26 0.1E-3\nI11 0 27 0.1E-3\nE4 28 4 26 27 0.025\nG2 29 4 24 25 2.9E-7\nR22 2 6 100E6\nE5 30 0 21 0 1\nE6 31 0 9 0 1\nE7 32 0 33 0 1\nR30 30 34 1E5\nR31 31 35 1E5\nR32 32 36 1E5\nR33 0 34 10\nR34 0 35 10\nR35 0 36 10\nE10 37 3 36 0 0.01\nR36 38 33 1E3\nR37 33 39 1E3\nC6 30 34 0.2E-12\nC7 31 35 0.2E-12\nC8 32 36 0.2E-12\nE11 40 37 35 0 0.8\nE12 29 40 34 0 0.8\nE14 41 9 21 9 0.5\nD11 18 21 DD\nD12 9 18 DD\nM1 42 43 17 17 NOUT L=3U W=80U\nM2 44 45 16 16 POUT L=3U W=80U\nM3 46 46 20 20 POUT L=3U W=80U\nM4 47 48 10 10 PIN L=3U W=110U\nM5 49 50 12 12 PIN L=3U W=110U\nM8 51 51 22 22 NOUT L=3U W=80U\nR43 52 45 100\nR44 53 43 100\nG3 18 41 54 41 0.2E-3\nR45 41 18 120E6\nC12 19 23 10E-12\nR46 9 47 2E3\nR47 9 49 2E3\nC13 47 49 1E-12\nC14 29 0 4E-12\nC15 28 0 4E-12\nC16 23 0 0.5E-12\nD13 43 7 DD\nD14 55 45 DD\nQ15 55 15 21 QLP\nV18 29 56 0\nM19 57 58 21 21 PIN L=6U W=500U\nE17 39 0 29 0 1\nE18 38 0 4 0 1\nM23 58 58 21 21 PIN L=6U W=500U\nV21 57 11 0\nR59 23 44 1\nR60 42 23 1\nJ1 59 29 59 JNC\nJ2 59 28 59 JNC\nJ3 28 60 28 JNC\nJ4 29 60 29 JNC\nC21 29 61 2E-12\nE20 62 41 49 47 1\nR62 62 54 1E4\nC23 54 41 0.1E-12\nG7 63 41 18 41 -1E-3\nG8 41 64 18 41 1E-3\nG9 41 65 51 9 1E-3\nG10 66 41 21 46 1E-3\nD17 66 63 DD\nD18 64 65 DD\nR66 63 66 100E6\nR67 65 64 100E6\nR68 66 21 1E3\nR69 9 65 1E3\nE23 21 52 21 66 1\nE24 53 9 65 9 1\nR70 64 41 1E6\nR71 65 41 1E6\nR72 41 66 1E6\nR73 41 63 1E6\nG11 6 2 67 0 315E-6\nR75 40 29 1E9\nR76 37 40 1E9\nR77 3 37 1E9\nR78 4 28 1E9\nR79 41 54 1E9\nR81 52 21 1E9\nR82 9 53 1E9\nR83 33 0 1E9\nG14 58 9 67 0 55U\nG15 46 51 67 0 80U\nE48 68 18 67 0 30\nE49 69 41 67 0 -30\nV49 70 69 15\nV50 71 68 -15\nR127 68 0 1E12\nR128 69 0 1E12\nM41 41 71 18 72 PSW L=1.5U W=150U\nM42 18 70 41 73 NSW L=1.5U\nR129 72 0 1E12\nR130 73 0 1E12\nM43 74 5 9 9 NEN L=3U W=300U\nM44 75 76 9 9 NEN L=3U W=3000U\nR131 74 21 1E4\nR132 75 77 1E6\nV51 77 9 1\nM45 78 78 21 21 PEN L=6U W=60U\nM46 5 78 21 21 PEN L=6U W=60U\nI20 78 9 0.1E-6\nC26 5 0 1E-12\nE50 67 0 79 9 1\nV52 75 79 1.111E-6\nR133 9 79 1E12\nC32 21 74 3E-15\nC33 77 75 3E-15\nI21 6 2 30E-6\nL1 23 1 4E-9\nR150 23 1 400\nV78 21 59 0\nV79 60 9 0\nR155 46 21 1E8\nR156 9 51 1E8\nR157 17 43 1E8\nR158 16 45 1E8\nRG1 0 67 1E9\nR159 61 28 100\nR225 50 28 25E3\nR226 48 56 25E3\nM48 80 81 2 2 NIQS L=3U W=1000U\nR297 80 6 61.5E3\nE94 81 2 67 0 2\nM49 82 74 9 9 NEN L=3U W=300U\nM50 76 82 9 9 NEN L=3U W=300U\nR298 82 77 1E4\nR299 76 77 1E4\nC35 77 82 40E-12\nM51 83 84 85 85 NIN L=3U W=110U\nM52 86 87 88 88 NIN L=3U W=110U\nR300 89 85 2\nR301 89 88 2\nR302 83 21 2E3\nR303 86 21 2E3\nC36 83 86 1E-12\nG36 18 41 90 41 0.2E-3\nR304 41 90 1E9\nC37 90 41 0.1E-12\nE97 91 41 86 83 1\nR305 91 90 1E4\nV115 92 56 1E-3\nR306 28 87 25E3\nR307 92 84 25E3\nM53 93 94 95 95 PIN L=6U W=500U\nR308 95 57 2E3\nV116 21 94 1.25\nM54 93 93 9 9 NIN L=3U W=500U\nM55 89 93 9 9 NIN L=3U W=500U\nE98 21 14 6 16 1\nE99 13 9 17 2 1\nC105 77 76 130E-12\nR233 78 21 1E12\nR334 93 9 1E12\nR335 58 21 1E12\nR336 94 21 1E12\nR337 2 81 1E12\nG37 28 0 96 0 6.6E-12\nI48 28 0 1E-12\nI49 0 97 1E-3\nD46 97 0 DD\nV119 97 98 0.7\nR633 0 98 1E6\nE100 99 0 98 0 -571\nR634 0 99 1E6\nD47 100 96 DD\nV120 99 100 83.5\nG38 29 0 96 0 6.6E-12\nI50 29 0 1E-12\nR635 0 96 1E6\nR636 96 100 1E11\n.MODEL DVN D KF=8E-12 IS=1E-16\n.MODEL DD D\n.MODEL DIN D\n.MODEL QLN NPN\n.MODEL QLP PNP\n.MODEL JNC NJF\n.MODEL POUT PMOS KP=200U VTO=-0.7\n.MODEL NOUT NMOS KP=200U VTO=0.7\n.MODEL PIN PMOS KP=200U VTO=-0.7\n.MODEL NIN NMOS KP=200U VTO=0.7\n.MODEL NIQS NMOS KP=200U VTO=0.7 IS=1E-18\n.MODEL NEN NMOS KP=200U VTO=0.5 IS=1E-18\n.MODEL PEN PMOS KP=200U VTO=-0.7 IS=1E-18\n.MODEL PSW PMOS KP=200U VTO=-7.5 IS=1E-18\n.MODEL NSW NMOS KP=200U VTO=7.5 IS=1E-18\n.ENDS\n* END MODEL TLV2371
TEXT -1536 0 Left 0 !.LIB TLC074.mod
TEXT -1432 -216 Left 0 !.LIB TLV2371.mod
TEXT -1128 -552 Left 0 !.INC AD8646.mod