Subversion Repositories HomeAutomation

Rev

Rev 1199 | Blame | Compare with Previous | Last modification | View Log | SVN | RSS feed

  1. #ifndef TWI_MASTER_H
  2. #define TWI_MASTER_H
  3.  
  4. /*****************************************************************************
  5. *
  6. * File              TWI_Master.h compiled with gcc
  7. * Date              Dec 2, 2008
  8. * Source            Modified from AVR315 - TWI Master Implementation
  9. * Supported devices : All devices with a TWI module can be used.
  10. *                     The example is written for the ATmega168.
  11. *            Requires that clock be set at 4MHz.
  12. *
  13. * This is the hardware driver for the TWI module implementing the I2C bus.
  14. * 12/19/08  Added Random (memory) Read function.        -jkl
  15. * 5/3/09    Revised to allow Random Read with more than one address byte. Made buffer
  16. *               length 128 data bytes. -jkl
  17. *
  18. ****************************************************************************/
  19.  
  20. /****************************************************************************
  21.   TWI Status/Control register definitions
  22. ****************************************************************************/
  23. #define TWI_BUFFER_SIZE 131   // Slave Address + Memory start address (2 bytes) + 128 data bytes (message size)
  24.  
  25. // For 4MHz clock, data rate will be 100Kbps with 0x0C.
  26. // Using 0x0C and an 8MHz clock, data rate will be 200Kbps. If only 100Kbps is required,
  27. //  change this value t0 0x20.
  28. #define TWI_TWBR            0x0C        // TWI Bit rate Register setting.
  29.                                         // See Application note for detailed
  30.                                         // information on setting this value.
  31. // Not used defines!
  32. //#define TWI_TWPS          0x00        // This driver presumes prescaler = 00
  33.  
  34. /****************************************************************************
  35.   Global definitions
  36. ****************************************************************************/
  37.  
  38. union TWI_statusReg                       // Status byte holding flags.
  39. {
  40.     unsigned char all;
  41.     struct
  42.     {
  43.         unsigned char lastTransOK:1;
  44.         unsigned char memRead:1;
  45.         unsigned char unusedBits:6;
  46.     };
  47. };
  48.  
  49. extern union TWI_statusReg TWI_statusReg;
  50.  
  51. /****************************************************************************
  52.   Function definitions
  53. ****************************************************************************/
  54. void TWI_Master_Initialise( void );
  55. unsigned char TWI_Transceiver_Busy( void );
  56. unsigned char TWI_Get_State_Info( void );
  57. void TWI_Start_Random_Read( unsigned char * , unsigned char, unsigned char );
  58. void TWI_Start_Read_Write( unsigned char * , unsigned char );
  59. unsigned char TWI_Read_Data_From_Buffer( unsigned char *, unsigned char );
  60.  
  61. /****************************************************************************
  62.   Bit and byte definitions
  63. ****************************************************************************/
  64. #define TWI_READ_BIT  0       // Bit position for R/W bit in "address byte".
  65. #define TWI_ADR_BITS  1       // Bit position for LSB of the slave address bits in the init byte.
  66.  
  67. #define TRUE          1
  68. #define FALSE         0
  69.  
  70. /****************************************************************************
  71.   TWI State codes
  72.   Note: 3 lsbs are for prescale value and should be masked out. (12/2 -jkl)
  73. ****************************************************************************/
  74. // General TWI Master staus codes                      
  75. #define TWI_START                  0x08  // START has been transmitted  
  76. #define TWI_REP_START              0x10  // Repeated START has been transmitted
  77. #define TWI_ARB_LOST               0x38  // Arbitration lost
  78.  
  79. // TWI Master Transmitter staus codes                      
  80. #define TWI_MTX_ADR_ACK            0x18  // SLA+W has been tramsmitted and ACK received
  81. #define TWI_MTX_ADR_NACK           0x20  // SLA+W has been tramsmitted and NACK received
  82. #define TWI_MTX_DATA_ACK           0x28  // Data byte has been tramsmitted and ACK received
  83. #define TWI_MTX_DATA_NACK          0x30  // Data byte has been tramsmitted and NACK received
  84.  
  85. // TWI Master Receiver staus codes  
  86. #define TWI_MRX_ADR_ACK            0x40  // SLA+R has been tramsmitted and ACK received
  87. #define TWI_MRX_ADR_NACK           0x48  // SLA+R has been tramsmitted and NACK received
  88. #define TWI_MRX_DATA_ACK           0x50  // Data byte has been received and ACK tramsmitted
  89. #define TWI_MRX_DATA_NACK          0x58  // Data byte has been received and NACK tramsmitted
  90.  
  91. // TWI Miscellaneous status codes
  92. #define TWI_NO_STATE               0xF8  // No relevant state information available; TWINT = �0�
  93. #define TWI_BUS_ERROR              0x00  // Bus error due to an illegal START or STOP condition
  94. #endif /* TWI_MASTER_H */
  95.